It's a long time ago you wrote that message into Expedition community but I hope this is still a functionnality that should be included into Expedition.
Compared to Pads layout, it seems that most of Layout Driven Design (LDD) functions lacks at Expedition, or we at least didn't find those :
- how to create a PCB without any schematic
- how to add manually a component
- how to set a net to a specific pad of a component
In our case we are working on component packaging design. Using pads we were testing the routing capability of a chip in certain conditions ( change of ballout, of PCB technology, etc). Because lots of parameters, especially ballout of component, is changing from one day to the other, we were accustomed not to design any schematic but directly do the pin mapping and signal assignment into PCB.
It doesn't seem to be possible in Expedition, but this is a new tool for us. Could you please confirm that we didn't miss anything ? Could you share your view on future development of Expedition regarding LDD ?
Thank you for advance and best regards.
I will let Jerry answer the questions on LDD for you, but I did want to comment on "Ballout Studies" in Expedition. In my history of being a PCB Designer and Design Manager, I developed a process used by several major chip companies for doing Ballouts. Expedition does them very well, and is quite possibly the most capable at them. Using the DxDesigner and Expedition tools within the Expedition Enterprise Flow you have the capability to Collaborate during the Ballout process. This allows the engineer to make changes to the Circuitry while the PCB Layout designer is working on the layout - through the same single database of constraints. Forward and Backward Annotation is as simple as a Mouse Click when changes are required to be updated between the tools.
Here is a brief description of what was done.
1. Engineer creates a Full, but Baseline statring point schematic for the Ballout Study
2. The Chip being Optimized in the Ballout was placed as a Single Symbol on the schematic with ALL Pins made Swappable (This symbol can be large, but it is just a Ballout Symbol)
3. Create a Cell footprint of the Chip to be Optimized, I suggest a Full Array of balls, even if there will be gaps in the final array.
4. On the PCB Layout, place your Peripheral Circuits and your Main chip for optimization as needed, as if a real layout.
5. Use the "Outside-In" approach to routing the pcb. Route the Peripheral Circuits, and then route inward to your Ballout Chip.
6. Since your Footprint is fully Swappable, swap the pins as needed to untangle your routing for optimal layout.
7. Back Annotate final swaps to the DxDesigner schematic and symbol.
8. Export the symbol in DxDesigner, and fragment it into functional blocks as you need in your library. This will be the final symbols used in your Final schematic.
My previous design team used this method on every Ballout Study, and took weeks off of the processes used in other tools.
Note: If doing FPGA optimization, check out IO Designer. It is fully integrated in the EE Flow, and automates the process for you.
If you have any questions on the method, please feel free to email me on a separate thread.
Thank you vern,
You're way of managing ballout analysis seems to be a good idea. We will try that for a future chip.
We're going on our way of using Expedition, and in different situations, we would like some layout driven function into Expedition.
Latest time was about putting some footprints onto the same pcb in order to compare and check different one, or being able to do some printing of footprint group for reference.
I don't remember of other examples, but we had some.
Seems not to be so important, but this should be a real time saved. This was so easy in Pads ...
Can you send me your direct email contact please. I would like to put you in touch with another member at Mentor who may have some ideas to help your needs. Please send me an email, you can find my contact info in my profile page.