You won’t be able to achieve your target impedance goals if you keep the FB in your PDN. Typical values for a FB are:
· DC Resistance = 0.2 ohm
· Impedance @100MHz 120 ohm
With a 3A of current that flows through this FB, you’ll get a significant voltage drop across it.
I noticed that you have posted same message on the [SI-LIST] and I replayed to it. However as this is HyperLynx related topic I believe that it can be better addressed in this forum. Consequently here are few additional comments:
- If your question is about how to use the tool to perform decoupling analysis, then based on the HL terminology, a sink refers to a DC Power Pin Model and implies DC Drop Analysis. For decoupling analysis you don’t have to assign a DC Power Pin Model, so you don’t have to “take FB as one of the sink with 3A of current”. Moreover the decoupling analysis does not care if the sink draws 1A, 2A ore more. This matters only while calculating the target impedance. The only think you need to do is to assign VRM, decoupling capacitor models and proper stack-up definition. The tool will provide you the impedance at the FB observation pin assuming that you have checked it under the corresponding Decoupling Wizard menu.
- As it is pointed out on a revived post if you really want to include FB on your analysis you will have to perform Spice simulations in LineSim. See the MGC TechNote MG502177.
- From a circuit standpoint Ohm’s low still applies, so the voltage drop across FB is null only if the FB’s impedance is zero across the whole frequency range of interest (assuming a 3A current that flows through the FB). A short does meet this requirement better than a ferrite bead.
Cristian, thanks a lot for guidinng me on this topic,
In my last post i didnt mention the Rating of the FB.
My FB details are:
26 Ohm @ 100Mhz
DC resistance = 0.007ohm
We are using FB to suppress the noise of n1 to enter n2.
since n2 is the core voltage of IC1, so we want a noise free Plane below it.
My query was
for doing Decoupling analysis of n2 we treated FB as VRM and optimized the DECAPs to make impedance graph less than Target impedance below IC1,
Now While doing Decoupling analysis of n1, i m treated FB as one of the IC which is drawing 3A of current from the plane.
since FB is drawing more current than IC2, so target impedance was calculated as per the current of FB. which is coming out to be 22.92 mOhm.
In order to keep the impedance graph of n1 below target impedance we placed DECAPS at the input of FB and succeed in lowering the Impednce Graph near FB.
is my approch correct?
Based on the requirements that you have provided I would say that the best design solution for this case would be to remove the FB and make sure that the PDN at node (n1) meets the target impedance calculated using the sum of the two currents (IC1 and IC2). As the margin noise is the same for both nodes (2.5% of 1.375V), even though “the noise from n1 enters n2”, it shouldn’t harm IC2 (which will still be below the threshold).
Now from a simulation point of view treating the FB as VRM is completely wrong unless the two have same impedance profile over the whole frequency range of interest. However the output impedance (on the KHz/MHz range) of a VRM is typically low (in the order of few mohms), while the impedance of the FB goes quickly up to few ohms. On the real circuit that contains the VRM, decoupling caps at node n1, FB and decoupling caps at n2, the simulated PDN impedance looking into the IC1 power pins will see the VRM in series with the FB and the resulting impedance profile will be dominated the by the FB’s impedance as it is few orders of magnitude higher that the VRM impedance. If you replace the FB with a VRM you basically remove the FB from the analyzed circuit and this is why you have managed to “make the impedance graph less than Target impedance below IC1”. Again the proper way to simulate this in HyperLynx is using the method depicted in the MGC TechNote MG502177.
I am attaching for you a pdf document that shows few screenshots from Spice simulations that I run to exemplify the above explanations. You can notice that adding the FB in the PDN actually increases the noise at IC1 power pins due to the anti-resonance peak formed by the FB’s inductance and the IC’s decoupling caps.
If you want to learn more on this topic you can read the following documents:
- Altera’s AN583 AppNote: “Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs”
- “PDN Application of Ferrite Beads”, by Steve Weir, DesignCON 2011
- “Right the first time” – A practical handbook on high-speed PCB and system design, by Lee. W. Ritchey, Vol.2.
PDN Spice Sims.pdf 137.7 KB