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- The initial delay delta is calculated as (tDQSDQ(max) – tDQSDQ(min))/2 (See Mentor’s AppNote 10685 – “Explanation of the HyperLynx DDR Wizard Results Spreadsheets”).
- It really depends on many factors as data rate, corner case, modeling accuracy and design requirements. In general speaking this is a small number for address signals. If the hold margin is a lot bigger, you might want to increase the length of the address lines to get larger set-up margin.