1 Reply Latest reply on Feb 12, 2014 7:04 AM by cristian.filip

    query regarding DDR3 Batch mode simulation




      Please clarify the following queries:


      1. Please clarify the term  Initial Delay Delta, [ps] in DDR3 Batch simulation.

      2. For Address signals the simulation set-up margin is 16ps. How to interpret this value whether it is good or at the edge??


        • 1. Re: query regarding DDR3 Batch mode simulation
          1. The initial delay delta is calculated as (tDQSDQ(max) – tDQSDQ(min))/2 (See Mentor’s AppNote 10685 – “Explanation of the HyperLynx DDR Wizard Results Spreadsheets”).

          2. It really depends on many factors as data rate, corner case, modeling accuracy and design requirements. In general speaking this is a small number for address signals. If the hold margin is a lot bigger, you might want to increase the length of the address lines to get larger set-up margin.