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I believe that the overall thermal pad size does matter. Viewing the padstack or Gerber on the computer everything is in perfect alignment, it isn't that way on the final board. There is drill deflection, layer misalignment, etc. I set the plane thermal diameter to be the same size as the plane clearance and the tie width to total 60% of the Pad diameter. Below is an example copied from my padstack calculator/generator program.
If the padstack is to be used on a Press-fit component I use a Burried Thermal, since the thermal ties are there to limit heat loss during soldering.
Thank you for the reply and the information. Helpful.
One thing that I am noticing is that it appears that the diameter of the thermal pad is irrelevant.
I have a padstack which consists of a 1mm PTH with 65thou pads (all layers).
At first I set my thermal pad as 65thou with 20thou ties and 10thou clear.
This then does what we require on the layout ok.
However if I then go back and reduce the overall size to a smaller value e.g. 30thou, so that my settings are like this.
This then seems to have no effect on my layout or gerber outputs.
Currently in our library we have hundreds of different pad sizes for through hole components, what I would like to do is define a single thermal pad size say 30th/20th/10th as per the second image above and use this for all our padstacks within the library.
Is there any problem in defining the thermal pad this way?
I'm not sure what you mean that "This then seems to have no effect on my layout or gerber outputs". Changing the parameters will absolutely have an effect on the gerber output. Here is a preview of one of my padstacks:
You can see that the pad size on the negative thermal is the same as the positive pad size. Since the pad size is based on the annular ring requirements it should be a consistant size based on the finished hole size. I use IPC-2222, 9.1.2 for my thermal tie calculation: "Total thermal width = 60% of land size". For your 65 pad below I would use: 65 X 0.60 = 39, 4 thermal ties, 39 / 4 = 9.75. So I would round up and use 10 mil thermal ties for a 65 pad.
Your example shows a 30 diameter reduced by a gap of 10 = 20. So it has effectively a 20 pad with 20 thermal ties. That is the equivalent of a burried thermal and will not do anything to mitigate thermal loss during solder. If that is the case then you could just use the (Buried Thermal) pad definition and get the same results. That is asking for problems in manufacturing and especially for rework. You may get away with that when the entire board is preheated before soldering but rework would be a nightmare.
Review your proposal with your assembly house, I'm sure they would have issues with it.