3 Replies Latest reply on Feb 6, 2014 7:20 AM by clint.cote

    Guideance on Plane Thermal in Padstack Definition

    greg.hall

      We want to add on all our through hole padstacks a plane thermal pad. Thereby elimininating the need for the pcb designer to setup the plane definitions manually within the layout.

       

      As is standard we have several through hole padstack with various sizes of top/bottom pad.

       

      My question is that when I define my thermal pad does the overall size matter?

       

      For example we have a padstack with a round 100thou pad and for a trial I have added a thermal pad which is only 65thou round (width 20thou, WebClear 10thou)

      When I then bring this modified padstack onto my layout, the thermal ties appear to work fine.

       

      This leads me to the conclusion at the moment that for the thermal pad the size of the pad does not matter, it could be 40thou and the thermal ties appear the same.

      By not having the thermal pad defined as round 100thou what if any problems is this likely to cause going forward to gerbers and fabrication?

       

      We currently use DxDesigner/Expedition 7.9.1 flow. Therefore is this a bug in this version or how this is supposed to work.

       

      Any help and guidance as to what I should be specifing in our library would be of help.

        • 1. Re: Guideance on Plane Thermal in Padstack Definition
          clint.cote

          I believe that the overall thermal pad size does matter.  Viewing the padstack or Gerber on the computer everything is in perfect alignment, it isn't that way on the final board.  There is drill deflection, layer misalignment, etc.  I set the plane thermal diameter to be the same size as the plane clearance and the tie width to total 60% of the Pad diameter.  Below is an example copied from my padstack calculator/generator program.

           

          Padstack.jpg

          If the padstack is to be used on a Press-fit component I use a Burried Thermal, since the thermal ties are there to limit heat loss during soldering.

          1 of 1 people found this helpful
          • 2. Re: Guideance on Plane Thermal in Padstack Definition
            greg.hall

            Hi Clint,

            Thank you for the reply and the information. Helpful.

            One thing that I am noticing is that it appears that the diameter of the thermal pad is irrelevant.

            I have a padstack which consists of a 1mm PTH with 65thou pads (all layers).

            At first I set my thermal pad as 65thou with 20thou ties and 10thou clear.

            Capture.JPG

            This then does what we require on the layout ok.

            However if I then go back and reduce the overall size to a smaller value e.g. 30thou, so that my settings are like this.

            Capture2.JPG

            This then seems to have no effect on my layout or gerber outputs.

             

            Currently in our library we have hundreds of different pad sizes for through hole components, what I would like to do is define a single thermal pad size say 30th/20th/10th as per the second image above and use this for all our padstacks within the library.

            Is there any problem in defining the thermal pad this way?

            • 3. Re: Guideance on Plane Thermal in Padstack Definition
              clint.cote

              I'm not sure what you mean that "This then seems to have no effect on my layout or gerber outputs".  Changing the parameters will absolutely have an effect on the gerber output.  Here is a preview of one of my padstacks:

              ThermalPad.jpg

              You can see that the pad size on the negative thermal is the same as the positive pad size.  Since the pad size is based on the annular ring requirements it should be a consistant size based on the finished hole size.  I use IPC-2222, 9.1.2 for my thermal tie calculation: "Total thermal width = 60% of land size".  For your 65 pad below I would use:  65 X 0.60 = 39,  4 thermal ties, 39 / 4 = 9.75.  So I would round up and use 10 mil thermal ties for a 65 pad.

               

              Your example shows a 30 diameter reduced by a gap of 10 = 20.  So it has effectively a 20 pad with 20 thermal ties.  That is the equivalent of a burried thermal and will not do anything to mitigate thermal loss during solder.  If that is the case then you could just use the (Buried Thermal) pad definition and get the same results.  That is asking for problems in manufacturing and especially for rework.  You may get away with that when the entire board is preheated before soldering but rework would be a nightmare.

               

              Review your proposal with your assembly house, I'm sure they would have issues with it.