FPGA’s are no different than ASICs in this regards, so if you know how to simulate DDR interfaces you should be able to manage this situation. The main difference resides in the fact that the timing and pin out information is not available from data sheets, but it is design specific. Consequently you will need to ask the FPGA designer to provide you a customized IBIS model (see the FPGA vendor documentation) and either a timing model or the required timing information.
If you want to learn more, in addition to Mentor’s AppNotes and Technotes, check the FPGA vendors’ websites. Here are few documents that you might want to have a look at:
- Altera – “Dual DIMM DDR2 and DDR3 SDRAM Interface Design Guidelines”, AN-444-1.1 AppNote
- Altera – “Design Guidelines for Implementing DDR3 SDRAM Interfaces in Stratix III Devices”, AppNote 436
- Altera – “DDR3 SDRAM Interface Termination and Layout Guidelines”, AN-520-1.1 AppNote
- DesignCon 2008, “Challenges in implementing DDR3 memory interface on PCB systems: a methodology for interfacing DDR3 SDRAM DIMM to an FPGA”, by Phil Murray, Altera Corporation and Feras Al-Hawari, Cadence Design Systems, Inc.
- EETimes article, “Designing DDR3 SDRAM controllers with today’s FPGAs”
Mentor’s TechNote MG535965 provides a good checklist for the FPGA Memory Controller IBIS model quality.