2 Replies Latest reply on Feb 21, 2014 7:56 AM by nadovicc

    Using DxDesigner with Verilog -- beginner question


      I want to associate a verilog file with a DxDesigner symbol. This way I can wire together a bunch of

      these verilog gadgets and netlist out a top level Verilog file for synthesis and simulation.

      I believe this is possible but I can't find a tutorial or a document that explains how to

      use DxDesigner in this way.


      I did find in the DxDesigner manual a statement to the effect that I should "just drag and drop"

      the verilog file onto a schematic and the symbol will be automagically created. I do this and

      get "Syntax Error" even though the verilog is fine.


      Can anyone point me at basic instructions for doing this?




        • 1. Re: Using DxDesigner with Verilog -- beginner question

          Hi C,


          There is no need to associate any model to the symbols to generate a verilog netlist of a schematic. Just go to File->Export->Verilog Netlist... and one or more Verilog files will be generated (depending upon the options used) in a genhdl folder at the root of the project.

          As soon as you export a HDL netlist an HDL Design folder is created in the Navigator where you can find all generated or associated HDL files. The color of the file icon must be blue (and not grey) which indicates that the file can be found. You can set teh Search Path in the settings to eventually resolve a problem.

          Generation options can be found in the Export HDL section of the DxDesigner settings (Setup->Settings->Export HDL). These options allow you for example to generate empty modules, which can be quite convenient. Another useful option is the Down To level one which allows you controlling the netlister's depth. For example imagine you have a FPGA represented as a hierarchical block. You'd like the netlister to stop at the block level. Underneath you're likely to find the PCB symbols as well as some decoupling capacitors... that you don't want in your netlist. Tp manage that you set the Level property to Verilog on the block symbol and you set the Down To level option to Verilog too. It basically tells the netlister to stop at that level.

          You can indeed drag&drop a piece of Verilog into the schematic editor to automatically create a symbol whose pins will be based on the port definition in the HDL. At the same time the HDL model is automatically associated to the symbol through the Verilog File and Verilog Model properties (Simulation Model property is also usually used to specify if the model is Verilog or VHDL). Which version of DxDesigner do you use on which O/S?

          In order to manually assign a model to a symbol you set the Verilog File property to the model verilog file name (e.g. uart.v) and make sure it is seen by the tool (blue icon) prior to compiling all generated files through the provided ModelSim interface... provided you set up the Setup->Settings->HDL/FPGA Simulation->Integrated simulator setting properly... and you use ModelSim as a simulator. :-)

          Note that the model port definition must be in sync with the symbol pins when you associate a model to a symbol!


          I hope it helps.




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          • 2. Re: Using DxDesigner with Verilog -- beginner question

            Thanks for the tips. I can, indeed, create a verilog netlist from a tree of interconnected hierarchical blocks. That works. What I've been

            unable to figure out is how to embed some actual code in the terminal "leaves" of the tree.


            I can NOT drag and drop. When I do, it says "syntax error" in the log window even though the verilog is without doubt clean -- maybe it's expecting

            VHDL but the dropped file is Verilog.  Is there some setting for this? I can't find it.


            I'll try using some of the properties you note to manually bind Verilog code to symbols. Pity there isn't a simple "add verilog model" menu item.


            Pity there's no documentation, example, or tutorial on this feature.


            Version is 9.4


            PS: is there some way to specify a "constant" to drive a net? I suppose if I could ever figure out

            how to embed verilog code into a block I could make a module called "true" with one output assigned to 1'b1, but

            maybe there's a more direct way?