2 Replies Latest reply on Mar 12, 2014 12:14 PM by VinS

    IBIS Model Issue

    VinS

      I am trying to use zynq7.ibs in a hyperlynx sim for XC7Z020-2CLG484I and get :

       

      Warning: U1 pin D20 not loaded from C:\01A_AVR2B EOL PROCESSOR\HYPERLYNX\L31-35001-008A.ref
        Pin D20 of component ZYNQ7 has no model in file C:\MentorGraphics\9.0HL\SDD_HOME\hyperlynx64\extended_ibis\fpga\zynq7.ibs
        Or pin D20 types differ (e.g. POWER pin found where I/O pin required).

       

      This is happening for all the pins on this part. All other devices are simulating normally.

       

      I re-downloaded the model in case mine was corrupted, no change. I think it is something with the package.

       

      Anyone know how to make this work?

        • 1. Re: IBIS Model Issue
          cristian.filip

          The IBIS model you have is not ready to be used as it does not contain the FPGA custom pin out information. If you look at the [Pin] section of the model you will see a list of generic pins:

           

          |***********************************************************************

          [Pin]  signal_name          model_name

          1P   BLVDS_25_HR_P           BLVDS_25_HR

          1N   BLVDS_25_HR_N           BLVDS_25_HR

          2P   DIFF_HSTL_I_F_HR_P        HSTL_I_F_HR

          2N   DIFF_HSTL_I_F_HR_N        HSTL_I_F_HR

           

          A proper model should map the FPGA pins to signals and technology models:

           

          |***********************************************************************

           

          [Pin]  signal_name          model_name

          H14      FPGA_NRESET          LVTTL_S_12_TB_25

          T14      VIDEO_DAC_NSYNC      LVTTL_S_12_TB_25

          V19      VIDEO_DAC_NPSAVE     LVTTL_S_12_TB_25

          T5       SPI_NCS              LVTTL_S_12_TB_25

          L1       mcb3_dram_dqs_n(0)   SSTL15_OT50_LR_25

           

          Please notice the difference between the two models (first and second column).

           

          You can either manually create a customized IBIS model for your FPGA (not recommended) or you can use the IBISWriter utility to do it automatically. Please refer to the link below for more details:

           

          http://www.xilinx.com/support/answers/21632.htm

          • 2. Re: IBIS Model Issue
            VinS

            I thought something was not right with the model, Thanks for the help.