That is correct, the nets will be different at the schematic level in which the blocks are placed and the internal nets will get flattened by the netlister or packager depending on the floe you are using. One tip, freeze the block symbol to avoid inadvertent renaming of the pins. There are plenty of discussions around hierarchical design on this forum so do a search on hierarchy for more details and also look in the supplied documentation.
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I have posted an idea years ago but seems Mentor have no response by now. The idea is allowing flat netnames'suffix/prefix be same with Component Ref's sufix/prefix assigment. This make schematics clear and convinient to explore nets during layout phase.
Additionally, I also wish Dxdesigner can have an option to display flant netnames and Refs while descending dwon to the blcok.
Thanks, the freeze method worked.