Timing Model for TI DSP TMS320DM8148

Discussion created by ks.padmanabhan on Mar 20, 2014
Latest reply on Mar 23, 2014 by ks.padmanabhan



We have setup the HyperLynx tool for first time and have been reading about the tool and its usage from the boardsim user guide. We would be carrying out post layout analaysis for the DDR3 Interface in our PCB which uses the TI DSP - TMS320DM8148. We carried out some interactive simulation as a starting point and things are going on pretty good!

We have been trying to setup the HyperLynx DDR Wizard and just started collecting the information on data related to the timing model for the DDR Controller. We realised that the datasheet or the technical referance manual does not publish any information regarding the timing parameter not any timing waveforms for the DDR controller so that we could modify the ddr3_ctl.v default file.


Have any of you guys had a chance to work on this chip?If so,how did you manage to get the timing information? I have been in touch with the TI guys but they seem to indicate that the DDR controller complies with the JEDEC spec. If thats the case, can i just use the default timing model file?


I can aattach the datasheet/TRM if anybody wants to have a look at it. Alternatively, it is available to download in the TI website.



KS Padmanabhan