About the "Solution to Agilent Puzzle" document posting

Discussion created by steve_kaufer on Nov 3, 2008
Latest reply on Nov 5, 2008 by yu.yanfeng


To anyone out there who's interested in high-speed-analysis topics (especially SERDES) - or any observers who are just plain curious: What motivated the "Solution to Agilent Puzzle" document posting from Vladimir?



Those of you who watch the signal-integrity news group saw a recent posting from Agilent in the form of a "puzzle." (BTW, I hope that in the near future, this Mentor community can become as informative as the SI news group - actually, more informative, because let's be honest: the news group contains a fair amount of "blather" these days, mixed in with the occasional gems.) The goal was to take a set of supplied SERDES-channel S-parameters, and determine the characteristics of an equalizer that would open the channel's eye diagram. (The channel quality is such that without equalization, the eye is completely closed at 6 Gbps.)



I'm not exactly certain of Agilent's intention, but one can imagine that they're anxious to show how their tools can be used to simulate such channels, and design effective equalization. Well, Agilent: please get in line and try to join the club! In fact, in the Mentor high-speed group, we were only too happy to take up the challenge, since using our HyperLynx v8.0 beta software, it's easy to solve the puzzle. The reason is that v8.0 will essentially do all the work for you: we're offering a new capability to synthesize the optimal settings for a driver pre-emphasis or receiver-end equalization circuit, given a time-domain (pulse/step) response that characterizes your channel. Vladimir shows in his nicely written document the results of this process. Just for fun (to make the puzzle a little bit more challenging), we include the solutions for the channel unterminated (at the receiver end) and 50-ohm terminated. Obviously, the eye diagrams (as revealed by time-domain simulation with the optimized equalizer settings) are better for the terminated case, which has inherently less inter-symbol interference; but note that even in the unterminated case, it's possible to achieve a reasonably open eye, and even with only a very modest (from a circuit standpoint) 2-tap equalizer.



BTW, these are the types of powerful, automated solutions that we're driving hard for in our HyperLynx v8.0 software, and in all of our future high-speed-analysis offerings in general. SERDES is a major focus for us now, but so are power integrity, DDR2/3 verification, and nice integration with the Expedition PCB flow. All of these things are coming in the next release of HyperLynx. There are a rich set of topics here from which to show examples and discuss issues; I plan to do much more of that in the near future. I hope there are some community members out there right now interested in high-speed issues: this is the place to come to get informed about - and to have influence over - Mentor's analysis tools.