We have followed all the guidelines and routed the board for DDR3 (1600 speed, 1.5V).
For the 1st round, we simulated DDR3 without Crosstalk enabled. We had no violation and a positive margin of around 70ps for Read operation.
For the 2nd round, when we simulated with 40mV Crosstalk, we get a negative violation with around -500ps margin.
But in Boardsim, when I enable Crosstalk Simulation and set the threshold to same 40mV, I don't get any agressor for any of my DDR3 data lines.
Q1. In that case, how does the excel generated by DDRx wizard show a change in my timing margins?
End goal is to check the agressors which gives me that 40mV crosstalk and try to space out my signal to avoid that crosstalk.
Q2. Also for a read operation, when do we consider derating? Is it dependent on the controller vendor?
My understanding is the JEDEC derating is valid only for a write operation. Please let me know if that is correct.
Note that the negative violation of -500ps is observed only for 3 nets (out of 64 data lines) in Fast corner which is a bit confusing.