1 Reply Latest reply on May 23, 2014 5:39 AM by cathy_terwedow




               I was new to hyperlynx I was able to simulate processor ddr batch simulation from the app note provided by hyperlynx

      how to create timing model for fpga ,I was not able to find out the timming parameters provided in the app note from  the data sheet

      Please help me

      thanks and regards

      AGXIN MJ