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simulate fpga ddr batch simulation?

Question asked by agxinmj on Jun 1, 2014

Hai,       

             I need to do the si analysis for FPGA DDR3 ,I am using kintex 7 FPGA ,AND MICRON DDR3 , Ihave the IBIS MODELS of both the components ,

to perform timing model I dont have the timing model for fpga, the BATCH simulation tool ask for some timing parameters that are not available in the FPGA data sheet , these are the parameters that the timing tool requires

 

DDRx Timing Wizard Required Parameters
tCKAC
tCKCTL
tCKDQS
tDQSDQ
tDS
tDH

to derive this parameters this are the formulas




DERIVING tCKAC(MIN) AND tCKAC(MAX)
tCKtDDKHAS(pS)tDDKHAX(pS)_
3.00E+003950950
tCKAC(MIN)tCKAC(MAX)
-2048.5-950






DERIVING tCKCTL(MIN) AND tCKCTL(MAX)
tCKtDDKHCStDDKHCX
3.00E+003950950
tCKCTL(MIN)tCKCTL(MAX)
-2048.5-950



DERIVING tCKDQS(MIN) AND tCKDQS(MAX)
tCKtDDKHMH(MIN)tDDKHMH(MAX)
3.00E+003-600600
tCKDQS(MIN)tCKDQS(MAX)
-600600



DERIVING tDQSDQ(MIN) AND tDQSDQ(MAX)
tCKtDDKHDS, tDDKLDStDDKHDX, tDDKLDX
3.00E+003325325
tDQSDQ(MIN)tDQSDQ(MAX)
-1174.25-325






DERIVING tDS AND tDH
tCKtCISKEW(MIN)tCISKEW(MAX)
3.00E+003-390390
tDStDH
390390









SUMMARY(RESULT)
DDRx Timing Wizard Required ParametersMin (ps)Max (ps)
tCKAC-2048.5-950
tCKCTL-2048.5-950
tCKDQS-600600
tDQSDQ-1174.25-325
tDS390
tDH390

these are the parametes required from the data sheet of fpga but not available in fpga data sheet(if a ddr is connected to a processor these parameters are available for the processor in the data sheet) how to find this parameters for fpga

 

tDDKHAS
tDDKHAX
tDDKHCS
tDDKHCX
tDDKHMH
tDDKHDS, tDDKLDS
tDDKHDX, tDDKLDX
tCISKEW

 

Please help me in deriving the timing parameters of fpga

thanks and regards

AGXIN J

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