I am designing a board for my chip using ExpeditionPCB. I have drawn the schematic by DxDesigner, and then I place all the cells in ExpeditionPCB and let it auto-route all the parts.
My problem is, as shown in the attached screeshot picture, my auto-route function cannot complete. It always fails at 92.66% progress with an error report: "Add 1-4 via failed for net $1N503 when changing to layer 4, Visit message locationSMT Pin Top; IC1-33; net $1N503; loc: (1,339.37, 2,328.74); class: (Default)". In the attached screeshot picture, (1,339.37, 2,328.74) is the highlighted 3rd pin from right.
Acturally I have already drawn a "rule area" rectangle, in which the sizes of vias and traces have been reduced in CES, as shown in the attached screeshot picture (the blue narrow traces). I believe that ExpeditionPCB should have more than enough space to add any vias.
So why in my rule area only the blue traces have been narrowed according to my CES, leaving all the rest traces as wide as unconstrained? And why does my auto-route function fail at 92.66% due to adding via problems???
Any help would be deeply appreciated... Thanks a lot in advance!