Typically this is when a either the pin ot the net have different widths desfined based on the name, for example net name D[7:0] pin name D[6:0] the net is 8 bits the pin is 7 bits. Without a picture of your design or additional information it is not easy to provide a solution.
Attached is word document which shows the DRC window with the warnings displayed.
Then there are screenshots of the top level schematic which shows the bus connected between the two lower blocks.
Then I have screenshots of the lower level blocks which show the bus on the signals on it.
Hope this helps.
DRCOutput_problem.docx 63.7 KB
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Are you using Bus Contents (it looks like you are)? If so have they changed during the design process? If so you need to propagate the changes using Tools - Update other Objects - Bus Signals to ensure the 'contents' are the same across the hierarchy.
If you run packager does it flag any mismatches in hierarchy? If not then it looks like DRC-124 is incorrectly reporting this issue.
Yes correct I am using the Bus Contents.
Had not previously done the update other objects -> Bus Signals and Bus Rippers.
I have now done this action.
I have also repackged the design and it completes ok and does not report any mismatches in heirarchcy.
Therefore it must be that this is a false drc-124 report.