Pin order in common sub-circuits

Discussion created by kdoherty on Jul 16, 2014



A funny issue we have here with Calibre LVS setup. A toplevel LVS passes with my run.


However, another layout engineer runs the same toplevel LVS and his fails. It seems to be with std cell pin order. We have a std cell area @ the top level. The pin order for example for the cells are: A B C Z VDD VSS. However, we have used std cells in some macros. The netlist created for this macros has the same std cell defined but with a different pin order: A B C VDD VSS Z.


What are the options that controls how the sub macros pin connects. We have tried to run with the same run file etc but his still fails and mine still passes.


Thanks in advance