For DDR3 having data rate of 1600MT/S
DDR 3 1600MT, Fclock=800MHz
Address/Command=400MHZ@ 1T timing and =200MHz@ 2T timing
Control = 400MHz whatever 1T timg or 2T Timing
One thing i want to ask If for data clock is 800MHz then for address it should be same i.e.800MHz but its getting halved to 400MHz. why ?
we know With 1T timing, the address and command signals can be issued on rising edge of every clock cycle. so frequency of address signal getting again halved to 400MHz cant understand , someone please help me to understand the logic behind it .