1 Reply Latest reply on Aug 7, 2014 6:16 AM by jduquette

    stitching vias and associated copper


      I'm having a problem with stitching vias.  I have a device (an RF oscillator) which is packaged in a metal case with four mounting tabs (right-angle metal with a hole).  My decal has four terminals for the four tabs and I've added copper under the device which is associated with one of the tabs (All tabs connect to ground).


      I tried adding both copper and copper-pour regions(assigned to ground) on the bottom of the PCB, but when I try and add stitching vias, I get a via placement violation.  I can turn off Design Rule Check, but I would like to know how to do this properly so I don't get an error.

        • 1. Re: stitching vias and associated copper

          What version are you running?  I did this recently in 9.3 and 9.5 without issues.


          There have been a lot of discussions going back and forth about whether the thermals should be tied to the decal (thru hole pins) or left to the designer (vias).  When there are many vias in the pad I typically go the decal path.  It means I get a bunch of extra (ground) connections on the symbol in the schematic but I have a repeatable thermal setup for a part. When it is one or two vias I'll add them at the board level.