Issue is on a TOP with analog IP ( with voltage lables ) is that TOP is deriving voltage from tied-on nets connected to pins with high voltage markers.
When i load voltage rdb in calibre i see below messsage. I checked and found there is certain prescence set for deriving the voltage levels in my SVRF
oltage specified with marker is above specified range. See 'restriction' property for details.
My top is at lower voltage than IP voltage. Please suggest a method to override such prescedence and force the TOP design to be running at its designated voltage level.
A quick response is much appreciated ! Thanks.