i have still the same problem with the DDRx Simulation. Witch model do you use now?
We have worked with a couple of IC vendors to create some device-specific timing models for the DDR wizard. We also have an application note that explains how to create the controller timing model. See http://supportnet.mentor.com/reference/appnotes/10706.cfm and http://supportnet.mentor.com/reference/technotes/public/technote.cfm?tn=MG246877
If you are using another DDR controller and are not able to find or create the timing model, you can open an SR on SupportNet and we can help. Creating the timing model requires some knowledge of the DDR controller timing and operation, as explained in the application note referenced above.
Most of our controllers have been the Texas Instruments TMS320D643x family of DSP (DDR2 PHY) or the Xilinx Spartan 6 FPGA family. One of them was a custom ASIC controller (LPDDR), which presented the most problems. I think I worked with you Weston on that project?
Pulling out this thread from the past to see if you can help. I have also opened a new discussion topic on this subject in the forum but there hasnt been any response.
We are working on the TI's DSP TMS320DM8148 and unfortunately do not have the timing information with respect ot he DDR controller for setting up the timing model in DDR Wizard.
TI is not ready to share the details for some reason. I have attached the datasheet for this chip. There is also a Techinical Ref Manual but the file size is too big to be attached even after zipping. It anyway deals with more register level information for software.
Can you suggest any way out for this?
TMS320DM8148.pdf 2.7 MB