different reference is generated for the symbols that are mapped as a swappable gate to a single component
If the packaging is correct in a new design (as you state) then the most likely reason for the first scenario is that you have some other gates scattered around the design that are getting packaged into U19 along with these two gates. There are a number of options you can look at to figure out what is happening. Look at the spare gates report to see if U19 shows any spare slots, if there are none then it indicates that there are other parts elsewhere in the design. If this is not the case then you can try four other options, these are all either or scenarios:
1: Use 'Update local library data with newer central library data' in packager
2: Set the optimization scope in the packager dialog to Page - the packager will group symbols on the page first.
3: Assign a reference designator to the four symbols to force them into the same package
3: Assign a Pkg Group property to all four symbols with the same value (which can be a number or alpha value, eg. Pkg Group = A)
I placed only the gates simultaneously in a fresh page of a packaged schematic sill it is coming like as i mentioned in the attachment for this particular schematic alone
In your document you state it is working as expected in a new schematic so it points to two issues, either the original design has other gates that are being packaged together or in this design the packager is not seeing the latest information. Step through each of the suggested solutions and see which if any fix it. Most likely you have other symbols with reference designator U19 elsewhere on the schematic.
If none of these suggestions work then post a picture of how you have mapped the symbols to the part in the PDB entry.
thanks for your reply sir
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