I've found that the maximum skew between DQ signals and their corresponding DQS must be less than 5ps for ddr3-1066(I'm simulating a board with xilinx FPGA and this is what it's needed for virtex-6). now I have three questions:
1- what is the definition of the skew between DQ and DQS?
2- how can I achieve this? I mean simulating the board in hyperlynx, and setting the probe to the die, is only the first step. then I simulate every single DQ net in a bytelane and the corresponding DQS. Is it correct to simulate single DQ and then load them altogether to view their skew?
3- if it's correct, how can I achieve +/- 5ps? I mean the rise and fall time of each individual DQ is not the same, so de-skewing the waveforms in their rising edges will result another skew in the falling edge which is greater than +/-5 ps.
really appreciate any answer.