As you have noticed, this design is highly symmetrical. That means that starting from time 0sec, both capacitor will load equally and both will try to make the transistor flow, which in turn will release both capacitor.
The fact that in real life this circuit works is that perfect symmetry is broken by small differences of the symmetry given by small differences in resistance, capacitance and threshold values for the transistors. Once this source of asymmetry is present, eventually one of the halves will charge first and start the oscillation.
In a simulation environment you have at least two ways to counter this:
-one is to mimic this small asymmetry by giving small variation in the component values. (Be aware this will break the symmetry and also produce a slightly asymmentric output)
-the other way is to simulate that one of the capacitors has a different starting condition. You can add a voltage over the circuit at time 0sec. This will allow the symmetric design to start in an asymmetric state, and thus allow it to oscillate.
Hope this helps
I have already tried both your suggestions and not managed to get a satisfactory result. A no convergence error seemed to be the most popular result. However changing the transistor model to another general purpose type BC807 is giving me much better results. I am getting reliable oscillations now after adding an initial voltage condition. If you have any advice on dealing with no convergence errors or can point me to any documents on the subject that would be appreciated.