Once you have completed your layout with Pyxis Layout, you would use the Calibre tools to perform physical verification. You use Calibre DRC to check your layout against the foundry design rules. Once the layout is DRC clean, you use Calibre LVS to compare the layout to the schematic. If this process produces no errors, then you would output GDSII from Pyxis Layout. This is then used to fabricate the chip by the foundry. I believe this is what you mean by "die photograph", the GDSII data. Am I correct?