I've been using the DDRx Batch Simulation tool (HyperLynx 8.1.1) to simulate an implementation of DDR3 memory, and I noticed that the tool seems to be ignoring the differential thresholds defined in the IBIS model for the Micron memory I'm using, and is using 0V instead.
For single-ended signals (address, control, command, data), it seems to be using the correct VIH(AC) and VIL(AC) thresholds (VTTref +/- 160mV in this case) for determining setup and hold times. But for differential signals (clock and data strobes), it seems to be using Vdiff = 0 rather than VIH,diff(AC) and VIL,diff(AC) (+/- 320mV for this part) for determing setup and hold times. In my simulations, there is ~50 ps between Vdiff = 0 and Vdiff = +/- 320mV, so all setup and hold times reported in the results spreadsheets are off by ~50 ps. This is causing some of my data signal setup times to be reported as failures under worst-case conditions, when manual inspection of the waveform files shows that they are actually passing when using the correct differential voltage thresholds for the DQS signals.
Is this behavior expected? I checked the "Use all four receiver AC/DC thresholds" option in the DDRx Batch-Mode Wizard setup, and I assumed that they would be used for differential as well as single-ended signals.