I am using EE2007.9.4.
I have 4 DDR'S connected to processor in my design.
I need length report with fan-out length of all individual IC's.
Is it possible?
Thanks in advance.
select only the top layer traces and lock it delete all the remainaing layers traces by selecting only the innerlayers traces generate report or set constrain in ces for chip to chip now you will get the fan out length