Here is some AMPLE that creates an array. This may not do exactly what you need but it is an example you can build upon. This userware is considered freeware and is not part of the main product. It comes "as-is" without the standard support agreement. There is a README file inside after you untar.
I tried to use the files, which you sent me, but I am not able to open these files. However, I used function (in pyxis layout) ' add => make => array', but the function doing a block. After that, I tried to use the function 'edit => flatten' (one level) and I've got the array of cells, but there is no relationship between layout and schematic. Is there some trick to fix it?
Thanks a lot!
I you are using Pyxis Layout functions directly, then you should create your layout and connect it to the schematic. The easiest way to do that is from the Pyixs Project Manager. Select the cell where your schematic lives. Click the right mouse button over the cell and choose the "New-> Layout" menu as you see below. When the dialog appears in Pyxis Layout, just accept the defaults. Your new layout will be schematic driven.
I am using the Pyxis Layout almost every day. This is not a problem, I mean the creating new layout. My apologies, probably I don't explain my problem right way. Problem is, when I create a layout (this way which you mention) I've got cells in schematic and then I am placing cells, ports etc. There are the connection data between schematic instance and layout instance and then between cells and ports. Until now is ok, but when I place a cell and then I use function to create an array, I've got cells which are not in touch with schematics instances. For example a SRAM, which array contain 8x16 cells. There will be 127 unplaced cells. My question was, is there some tricks to fix it? Because, when I open LDL cockpit, there are unplaced instances (from schematic design) and placed instances, which I obtain using by the flatten function (edit => flatten) to apply SRAM array.
My point is to avoid manually placing big array or a vector of instances, because of save time.
Hello Lukas, were you able to solve it?
I am doing a CPU simple scalar, it executes a single instruction pero cycle. I am using leonardo to get the netlist and then Pyxis to create the layout.
However to create the netlist of any memory involved on this CPU the tool get stuck and that is because the logic elements are to many so it can be solved. That is why a memory compiler have to be used to solve it.
Currently I am using OpenRAM to generate it, but I need to create the
GDS Library Cells:
• Column-multiplexer (if needed)
So I can use an script in OpenRAM to generate any SRAM that I need.
What is your approach to do SRAM memories to create the layout and then attach to the rest of the circuit, in my case the CPU.
Thank you very much for your time,