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A crude way is to cut your length matching tolerance in half for each PCB. That way when they add they will still be in tolerance. Make sure you have some verification traces routed on your PCB (or panel).
This sounds tricky. Is your connector specified to support this? I'd hate to see a great layout with the connector as the weakest link.
Once you figure out the routing for each PCB I suggest you copy each design into a third PCB so you can have all the routing in one design and verify the simulation results. Then the only unknown is in the connector...
Disclaimer - While I've never done a DDR3 layout, this is from lots of RF experience.
Thanks. I like your idea. Unfortunately it's not that easy. The FPGA board is already laid out and somebody above me decided to not worry about length matching on that board. It was decided all length matching would be handled and accounted for on the DDR3 board. Yes, our connector is rated for this kind of speed. I like your final idea of copying it all to one big board for simulation. Very good idea.
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I've been using a spreadsheet to match lengths of traces for years, and it's not so bad when you get experienced at it. Many topologies can't be done just using PADS, like when you have series and parallel terminations, or lengths need to be matched both within a group and also group to group, or the total length is a combination of net lengths and pin pair lengths, or in your case, when you have to factor in a different board. I've done reference designs where I have to factor in die-to-ball lengths of the BGA. I've developed a method that makes the process straightforward and reusable, and the formulas can be as simple of complicated as you need.
There are several concepts you need to get comfortable with, but this will get you into the spreadsheet. This has taken me a long time to develop, so I may not be explaining this too well:
- Organize the nets that need matching into classes, and hopefully they're named so it's easy to do. If nothing else, this makes sorting and lookups easier.
- Route them making sure each group is using the same layers and via count, but not too tightly together. DDR3 is relatively nice, as there is no group to group requirement.
- Using the spreadsheet viewer of Route, create a new scheme for Nets that just includes net name, routed length, via count, and net class.
- You can copy and paste that right into a tab of a new spreadsheet. Use one tab for each board, and separate tabs for net lengths and pin pair lengths if you need them. Using separate tabs means you can add updated data with just another simple copy and paste.
- Copy the net names you want to match into the first column of a new tab.
- Use VLOOKUP to get the length values in a new column, and another column for the other board.
- Make a SUM column for the two lengths.
- Use conditional formatting to flag the high and low values to make them easy to see.
- Create a =(MAX-MIN) column to get the length difference.
- When you see the MIN and MAX lengths, you go back and shorten the longest route the best you can, then use that length for lengthening the shorter traces to get within range.
- Manually change the new lengths on the separate tabs, and the formulas will guide your progress, or just cut and paste all the nets at once be replacing the tab being referenced.
- Use conditional formatting to flag the lengths when they're within range. I make them green.
Hope this gets you in the right direction.
Thanks for the input. The procedure you outlined was pretty close to what I was planning. I've started the layout and the process is working. Unfortunately, the process lends itself to human error. I've already had to go back a couple of times and redo things because of mistakes I made.