I have a design with an FPGA and DDR3. The DDR3 is on a daughter board of the FPGA board. I'm starting layout of the DDR3 board. I have to length match the total length of the Address and Data lines from the FPGA to the DDR3 (across 2 boards). It looks like I'll have to set up length rules for each board, then export each trace's length to a spreadsheet and match them by hand. Does anybody know of a better way? My PADS Router package does not include autorouting with length rules.