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Simulation for PCIe Gen3 and SAS3.0 Interface

Question asked by ks.padmanabhan on Feb 24, 2015
Latest reply on Mar 1, 2015 by ks.padmanabhan



We are looking at simulating couple of high speed SerDes - PCIe Gen3 and SAS3.0. The end application is a MegaRAID PCBA. This is an add-on card through the PCIe interface to the host motherboard.

Eventhough we have worked on DDR3 simulation previously(using Interactive mainly and also DDR3 wizard to some extent), this is the first time some simulation on high speed SerDes is being done. From the reading I did for last couple of weeks, I find that the simulation methodology is totally different from DDR3.


I was able to download the PCIe Gen3 design kit and am currently going through to it especially PCIe3_ibis_ami_example.doc file. This is my starting point for PCIe Gen3 Simulation.


I have checked with Mentor support on SAS3.0 Design Kit and understand that there isn't one. What are the possible ways/options for me to carry out SI simulation on this interface? What sort of model files (IBIS-AMI?) would I be needing and how to build the simulation setup?


Any pointers to above would be helpful since I am very much on my own to go about this task and heavily reliant on LineSim/BoardSim userguides and Internet for this.