3 Replies Latest reply on Feb 26, 2015 12:21 PM by randall_myers

    IOD weird pin behavior on generated symbols


      I'm trying to use IOD to generate "generic" symbols for a 672-pin Altera SOC/FPGA. I'm getting really weird results with respect to pin numbers, when I generate the 8 symbols I defined in IOD (currently using 7.9.4 patched to near current level). On some of the symbols, the pin numbers are visible, are the correct size, and in the correct orientation. On others, the pin numbers are not visible, and when I select the pins and check the visibility, they are a different size, and are all at 0-degree rotation, even on pins that are vertical, and here's the strangest part, there are TWO pin number attributes for each pin!


      I'm not using the "symbol generator" in IO Designer, I've manually filtered/selected/placed pins to create the symbols. I've looked over the properties for these 8 symbols in IOD, and I can't see any differences in them, and I'm completely stumped as to why I'm getting these results when I export the symbols from IOD. Anyone ever seen something like this before? It's going to take so long to clean these symbols up, I don't think I'll end up saving time using IOD to create the symbols!


      Any ideas?


      Tom D.

      Aeroflex (A Cobham Company)

        • 1. Re: IOD weird pin behavior on generated symbols

          I have some ideas, but could be poking around in the dark without enough information.  I'm a bit foggy on IOD generating symbols but not using symbol generator.  Using generic symbols sounds like you are using the schematic update design process.  I have a cheat sheet that describes one way to design from choosing a part all the way through layout so you can clearly see what IOD does for you in this design flow.  Feel free to contact me to figure out how you want to use IOD.  If it includes using the IOD symbol generator, the confusing properties should get cleaned up when a new symbol set is written. 



          • 2. Re: IOD weird pin behavior on generated symbols


            I was basically just trying to use IOD to speed up the symbol generating process, as opposed to "starting from scratch" like I would do for smaller parts. It was just a way to get all the pins/pin names onto symbols, and IOD makes it pretty easy to filter based on bank number, Vcc, etc. Probably not going to use IOD for this device after this. Once the symbols were exported, I am using symbol editor to go in and clean up things a bit. It was then that I noticed the "weirdness". I'm starting to spend some time "hand-editing" for clean-up, so at some point, it's going to get to the point of not worth the effort to re-generate from IOD, because then I have to start my cleanup all over again. As I'm checking the pin names against the Altera pin-list, I see a lot of pin labels that aren't complete as far as second and third functions. At some point in the process, while trying to update the IOD parts, it told me it couldn't update unless the version of IOD was updated, but I can't do that until we're ready for everyone who uses Dx/Expedition is ready to update. We're still waiting to jump to xDxDesigner/Xpedition until we run at least one pilot design through. It might just be that this part is new enough that I just can't use IOD for it, until we've made that move. Not sure what to think at this point, but I think I'm done with IOD for now, too much time wasted already.


            • 3. Re: IOD weird pin behavior on generated symbols

              OK.  Sorry about the wasted time.  Next time you are playing in this sandbox, give me a ring and we could maybe share a webex to clear things up.

              -- Randall