I'm trying to use IOD to generate "generic" symbols for a 672-pin Altera SOC/FPGA. I'm getting really weird results with respect to pin numbers, when I generate the 8 symbols I defined in IOD (currently using 7.9.4 patched to near current level). On some of the symbols, the pin numbers are visible, are the correct size, and in the correct orientation. On others, the pin numbers are not visible, and when I select the pins and check the visibility, they are a different size, and are all at 0-degree rotation, even on pins that are vertical, and here's the strangest part, there are TWO pin number attributes for each pin!
I'm not using the "symbol generator" in IO Designer, I've manually filtered/selected/placed pins to create the symbols. I've looked over the properties for these 8 symbols in IOD, and I can't see any differences in them, and I'm completely stumped as to why I'm getting these results when I export the symbols from IOD. Anyone ever seen something like this before? It's going to take so long to clean these symbols up, I don't think I'll end up saving time using IOD to create the symbols!
Aeroflex (A Cobham Company)