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How to correctly model Altium NET TIES

Question asked by on Apr 9, 2015

I am new to Hyperlynx simulations.   Our board design was done with Altium and some of the DDR3 nets are using the Altium "net tie" to make matching net lengths easier.   I am wonder how this should be modeled in Hyperlynx?  For DDR3 simulations can I just make this a 0 ohm resistor so that it looks like a short?