0 Replies Latest reply on Apr 9, 2015 10:35 AM by dons@npe-inc.com

    How to correctly model Altium NET TIES


      I am new to Hyperlynx simulations.   Our board design was done with Altium and some of the DDR3 nets are using the Altium "net tie" to make matching net lengths easier.   I am wonder how this should be modeled in Hyperlynx?  For DDR3 simulations can I just make this a 0 ohm resistor so that it looks like a short?