In case others want to know the same:
Better explanation of the problematic:
What I want is to use only one FPGA and for this FPGA have more than one symbol. Since on this single FPGA the FPGA IP (e.g. MUX 8:1) is instantiated more than one time, I would like to have the same functional symbol instantiated more times and different PCB symbols created for each different instantiation of the functional symbol.
Example: I create a functional symbol MUX 8:1 with 13 functional pins (MUX_IN[0:7], MUX_OUT, MUX_ADDR[0:2], MUX_EN). Then I instantiate it 10 times in the same DxDesigner project and are all inside the same programmed FPGA. I/O Designer would assign then to the PCB symbols 10 physical pins for MUX_OUT[0:9], 10 physical pins for MUX_EN[0:9] 30 physical pins for MUX_ADDR[0:2][0:9] and 80 physical pins for MUX_IN[0:7][0:9].
Answer from support (Terry Penn):
The functional symbol in IOD is just a ‘hierarchical block symbol’ in DxDesigner, with no control other than the underlying pcb symbol. If you instantiate this functional symbol 10 times it will have the same pcb symbol(s) on the underlying schematic sheet – this is determined by the properties on the pcb symbol :
If you instantiate the functional symbol 10 times it would have the same pcb symbols beneath it, and this would cause the packager to specify 10 parts/cells. You would need to have 10 functional symbols in IOD with the appropriate pcb symbol(s) beneath each one. IOD follows a strict and non-flexible hierarchical symbol structure. There is no way, using a special property or suchlike, to define a different pcb symbol beneath multiple instances of the same functional symbol. The example below shows a database that has 3 functional symbols with various pcb symbols beneath each – this is similar to how you would create your set of 10 :
You would need to have func_1, func_2, func_3 . . . . func_10 functional symbols.