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I/O Designer: multiple instantiation capability

Question asked by alberto.rodrigues@advantest.com on Apr 10, 2015
Latest reply on Apr 10, 2015 by alberto.rodrigues@advantest.com

Hello,

 

We are developing a FPGA IP that will be instantiated multiple times within an FPGA. Is there a way to create just one functional symbol in I/O designer and instantiate it multiple times in DxDesigner?

 

Let me give an example. Let's suppose we are creating a 8:1 MUX on FPGA (Verilog). Let's suppose we want to instantiate this 8:1 MUX ten times. Is it possible to create in I/O Designer one single symbol and instantiate it multiple times?

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