I'm running into some compiling/synthesis errors using the Mentor Graphics Precision RTL Synthesis software.
I'm hoping someone can shed some light on these errors I'm getting.
I've been using Mentor Graphics "HDL Designer" and "Precsion RTL synthesis" and
recently I decided to try and compile and program a VHDL design onto an older Altera MAX 9000 series CPLD.
The EPM9560RC208 to be exact, which is a 208-Pin Quad Flat pack component.
The problem I'm having is that when I generate the entire precision synthesis flow and then execute the "Altera MAX_PLUS II" Place and Route
as shown in the Screen caps further below: I get this Place and Route Error for Generating the ACF file.
The problem is also that the Folder location of the Altera MAX+PLUS II software file called "setacf.exe" is located in the MAXplus II root directory on my computer.
However, the precision synthesis software keeps trying to execute it from a default location. (See the Screen caps).
It does this regardless of the fact that I provide the Root Directory location of the MAX plus II software within the Options menu.
As shown below:
I'm wondering if anyone knows why I'm getting this error? and how to get around this?
I tried posting this question on a few forums like edaboard.com to try and get some help...
but have yet to receive a response.
Any help in correcting this problem would be greatly appreciated.
Thank you again.