there are differences in the stackup edior that you open in PCB and HL Linesim and HL Boardsim.
This differences are dependent on the version that you have of the tools.
For this discussion I will assume that you have the latest version of PCB (EEVX1.1 or EEVX1) and the latest version of HL (v9.2 or v9.2upd1).
If you have older versions of the tools the situation is even worse.
IF you define a stackup in PCB the editor appears to be similar than the HL editor (This was the great step forward in VX.1) The difference is that in this stackup you are only allowed to have one prepreg between copper layer and the outer copper layer can not have a metalization layer.
If you move your design to HY by export it depends on the format you choose. If you choose hyp format then your stackup will revert to a defaul stackup with part of the info taken from the pcb. If you use cce format then most of the data is correctly transferred to HL.
In HL it is very important that for the prelayout simulation you use the "free form schematic" that generates ffs files. The advantage is that if you use the integrated stackup editor you can export or import a stk format to reuse the stackup. If you use the old tln format you loose this capacity. In both cases the stackup editor seem the same, and it allows to put more data than in PCB, here you can add more prepregs between copper and add metalization for the real simulation.
If you import the board (in cce or hyp) you can use the stk format to import the exact stackup from prelayout into boardsim and quickly start postlayout simulation. If you used the old prelayout format and you could not save the stackup, then in postlayout you have to reenter the stackup.
As of today there is no way to import a stackup stk into layout. You will always have to edit the stackup in PCB first and once in HL either correct the stackup or import/export to stk for later use or for postlayout simulation.
Hope this explanation helps.
Thank you for your fast response. I actually want to know what is the correct stackup ? . Which stackup details I should send to the manufacturer and simulations ?
the stackup that you put in HL or in PCB has to come from a Pcb manufacturer, or must have been validated by it. Otherwise you can "invent" a stackup that is not manufacturable.
For simulation always use the best possible stackup, that is most exact to the stackup that the board will be made of.
For manufacturing the stackup should be the exact rappresentation that you got from the PCB manufacturer.
For PCB you use an approximation, that is still relevant to the simulation stackup.
Hope this helps
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Thanks for your input. New to the VX release we actually have a way to bring in the HyperLynx stackup into Xpedtion. There is a command-line utility called "ImportStk.exe" located in SDD_HOME that lets you point at an STK file and transfer that stackup to the specified PRJ file. I have attached a screenshot below.
many thanks for this information. I was not aware of the fact that you could import stackups in PCB as of VX.1
I have tried it a little bit and I see the same limitation that is keeping PCB and simulation stackup separate, as described above.
In PCB you have the limitation that only one insulation layer can be used between metal layers, and metal layers can not have metallization.
If you try to import a detailed Hyperlynx stackup into PCB it will generally either fail with an error (if there are more prepregs) or import the wrong thickness of the metal layer and change the total thickness of the board. (See SR 2697221818)
This problem has been addressed with idea D12505 "Improve Expedition to allow to have more prepregs between copper layers" (please do support this idea by voting for it).
Using this utility you still have to have two separate stackups. One for simulation and documentation for production and the other for designing the PCB. And this was the original question of this thread. Which stackup is the "correct one?" The answer is both.