In VX.1 the 'Add Via' dialogue has had a lot more functionality added to it - you can use it to create freeform vias, stitch contours, stitch shapes, arrays, and radial arrays. We basically took a lot of the RF functionality and now provide it with the base license.
For EE7.9.5 I would recommend using Edit > Place > Vias to add the vias in there one at time. Make sure the 'Same net' checkbox is enabled from Setup > Setup Parameters > Via Clearances, and that 'Use Placement Outline as Via Obstruct' is not enabled within Editor Control. Also check the 'Trace to Any' clearances within CES as this is what the conductive shape is using.
If all else fails, you can create a Batch DRC area around the conductive shape and run checking just on that specific area to see what the violation is.
Hello thanks for your response
I see that this will improve a lot with VX.1 thats great, now i did try what you say, and i figure out something.
If i change the conductive shape to GND net and then do Edit-->Place-->Via--> and select GND in the via dialog i can place the via in the conductive shape.
If i do the same thing but having a Conductive shape on Net0 and also the via on Net0 i am not able to place the via.
hmm i guess there is a flag somewear.
Maybe you shouldn't consider Net0 as being "a net".
It is just a default flag for conductive features that DON'T have a net assigned.
I'm pretty sure you will not have a problem adding vias to actual nets.
I can confirm the behavior is the same in VX.1 for (Net0) - you should stick to a specific net assignment if possible.
The comments about Net0 are correct. We do not allow multiple Net0 objects to connect to each other which would be bad since unused pins in a part are Net0 and you would not want to connect them all together.
In the end you need to create a real Net for this. You could use an existing net or the option to create unique Net0-X nets (in the project integration dialog used during Forward Annotation) which would allow you to connect lets say Net0-5 conductive shape with another Net0-5 Via/Trace because this is how we support fanout of unused pins in parts for testing.
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