1 Reply Latest reply on Jul 5, 2015 9:20 PM by Vincent_Pinto

    Shielding in 3D




      I've made a shielded (coaxial) cable with an SMA connector at both ends, I'd like to make a 3D harness of it in Creo. Well the main problem is, that if I connect the shield to one of the pins (first picture), it's not exported to the .nwf file. However I can make a splice, and connect that to the pin (second picture, I named the wire SHIELD), with a different wire, while the shield itself wont  be exported, the splice is like a connector with one pin in the exported file. Like this, I have to import another model named as the splice, and place it somewhere in the 3D design for proper connection. In some cases, this would be alright, because usually you need a shield terminator and a different wire, to connect the shield, but in the case of the SMA or a BNC connector you connect it to the housing, without using any separate terminator. Is there a convenient way to solve this problem? By the way, I can export a VeSys 3D wiring file in .xml and the shield is exported to that file, just I cant use it in Creo, where or  how could I use this specific file? (in Creo there's an import option "Mentor Graphics" but it says invalid file for the VeSys 3D xml)









        • 1. Re: Shielding in 3D

          Most users typically do a sync from the VeSys wiring design to the VeSys Harness design to bring the multicore structure to the harness drawing, and they just need for the parent MC outer diameter to be exported in the nwf file so that it contributes to the true bundle OD in Creo.  For this reason, they typically don't care too much about the shielding in Creo.  However, for user that do care, we have a means to configure its export into the nwf.


          At <VeSys_install>\adaptors\resources is the vesys_bridge.properties file. In it, set property Shield_as_wire=true. This will convert that shield (in the first pic) to a wire and will export it (Remove_shield=false).  As you know, the nwf format does not support nestings within a MC instance, and so VeSys supports "flattening" it out. For this, set Flatten_out_nested_multicore=true.  Restart VDesign, so that the new values are read in. Export the nwf, and you will see that the shield is now exported.


          If you have MC nestings in VDesign, they will not be present in Creo, but the MC will be created to the OD of the parent level, thus giving you an assurance that the bundle OD in Creo is true to reality.  Eventually, when you do a sync of the wiring from VDesign to VHarness, the MC nestings in the wiring design will be replicated in the harness drawing.