6 Replies Latest reply on Nov 13, 2018 6:55 AM by weston_beal Branched from an earlier discussion.

    DDRx, considering package deskew


      Also check the probe location, DDRx batch simulation probably uses the die as probe location while the default setting in the scope is 'always at pin'

        • 1. Re: DDRx, considering package deskew

          Matthias, thank you for your post that help me to introduce my next question.


          I think that DDRx has the probe location only on PIN. All the timing included in the.cvs report are taken from PINS, but also all the timing included in the timing model files referring to pins. It couldn't be different since datasheets give timing only @ pins devices.


          My question is: working with a very high speed memory i have to deskew the package from the controller side ( the chip producer give to me all the delay due to wire bonding ecc,). Since DDRx is considering the timing on pins (for both driver and receiver), i get lots of errors in the reports due to large trace length mismatch. There is a way to overcame this issue in order to have a report that clearly shows the real problems?


          Kind Regards,


          • 2. Re: DDRx, considering package deskew

            Hi Oscar,


            You are right the default location is at the pin but you can you can override this in the ibis models:



            [Component]     7403398 MC452


            Si_location     Die | Optional subparameters to give measurement

            Timing_location Die  | location positions 





            |     Keyword:  [Component]

            |    Required:  Yes

            | Description:  Marks the beginning of the IBIS description of the integrated

            |               circuit named after the keyword.

            |  Sub-Params:  Si_location, Timing_location

            | Usage Rules:  If the .ibs file contains data for more than one component,

            |               each section must begin with a new [Component] keyword.  The

            |               length of the component name must not exceed 40 characters,

            |               and blank characters are allowed.


            |               NOTE: Blank characters are not recommended due to usability

            |               issues.


            |               Si_location and Timing_location are optional and specify where

            |               the Signal Integrity and Timing measurements are made for the

            |               component.  Allowed values for either subparameter are 'Die'

            |               or 'Pin'.  The default location is at the 'Pin'.



            Best regards,



            1 of 2 people found this helpful
            • 3. Re: DDRx, considering package deskew

              Can you explain, where and how to add the internal trace delays?

              • 4. Re: DDRx, considering package deskew

                The package trace delays are represented by the package model in the IBIS file. There are 3 different methods to specify the package models, each being more specific and, hopefully, more accurate; [Package], <R,L,C>_pin, or [Package Model].

                This article gives some information about the 3 methods. https://support.mentor.com/knowledge-base/MG76593

                You can also use [External Circuit] with [Circuit Call], but that is an advanced topic.

                The package model, however you have it defined, is always part of the circuit simulation. That means that the internal package delays are always included in the simulation. The difference is just where you measure timing, inside the package or outside.

                • 5. Re: DDRx, considering package deskew

                  Thanks but the article isnt helpful as there is no information about trace length.



                  |               typ             min            max

                  R_pkg        0.39277         0.042367         0.78319

                  L_pkg       2.479e-9        5.093e-10        4.565e-9

                  C_pkg      1.273e-12        8.187e-13       3.792e-12




                  [Pin]     Signal_name                     model_name                   R_pin       L_pin        C_pin


                  AA15    VDD_A35                            POWER                      0.00269    5.409E-11    1.329E-11



                  [Package Model] is not defined.


                  For me thats shows, that there are no internal trace length in this specific IBIS-File and i should define it in [Package Model]? Iam correct?

                  • 6. Re: DDRx, considering package deskew

                    When we work in signal integrity, we translate length into equivalent time. The package pin length is translated into a delay time defined by

                    sqrt( L * C ).

                    The delay of each pin is defined by L_pin and C_pin declared on each pin line in the [Pin] section. If those parameter values are not present then the general parameters, L_pkg and C_pkg are used. The [Package Model] syntax also is written in L and C, not length.