I am new to HyperLynx and I a have questions: Currency I am debugging a PCB where we have an FPGA interfacing with ram module. In the attachment I am trying something very basic but I cant seem to get the results I want. I am trying to relate the tdp value in the datasheet for a 3.3 LVTTL driver (low slew 12 mA) to a simulation in HyperLynx. When I do the simulation I get different results. Even after factoring the temperature coefficient in I still do not see the same rise time or output delay that the datasheet suggest in the simulation?
1) What am I doing wrong here ?
2) Also the termination wizard also suggests 1.183 ns driver transition time which is close to the simulated rise time which also doesn't correlate to any figure in the datasheet ?
The fpga u are using is pro asic 3e series
You are intrested in the timing parameters in the data sheet ?
the parameters seems to be the delay
The parameters shown in the datasheet snap seems to be like does't corresponds to raise time
place a resistor series to the driver instead of cap
and again run the scope and check check the raise time parameters are given in the datasheet ?