I have the following two plots (a) practical measurement and (b) simulated measurement. In hyperlynix I have made sure I used all the correct IBIS models and entered the PCB stack-up correctly. The circuit consists basically of a FPGA driving 5 daisy chained SRAMs address lines. The plots in this post is based on a single address line at the end of the daisy chain. The question here is the expected rise time is 900ps (800mV to 2V) and the measured rise time is 2ns (800mV to 2V). From the looks of it in simulation is basically a factor 2 out in terms of rise time, is there any way in which I can improve the simulations accuracy? I suppose I can add more capacitance on the bus in the free from schematic. This would make the batch simulation operation very difficult for the entire PCB.
I need fix this because some other simulations and piratical measurements also shows the same thing where the rise time is out by a factor of 2. It could be that some where there is a box unchecked in hyperlynx but I doubt it since the two plots are very similar in over and undershoot ... Any Ideas guys ?