AnsweredAssumed Answered

DDRx Batch Simulation Issue

Question asked by gottodo1 on Aug 7, 2015

Hello,

      I am trying to run a DDR simulation and I get the following errors: I have updated the IBIS file on the Processor IC to list the DQS & CLK signals as differential and I went into hyperlynx and used the net assign tool to set the clock to differential. I verified the VDD_DRAM  voltage at 1.35 & VTT_DRAM at 0.65power nets are assigned in hyperlynx so I'm stuck on what else it could be. I found a similar thread where it was power nets that were the issue but I'm not sure what other issues I could be seeing.  Does anyone have any ideas on what else I could be missing? The components for the clock are discrete resistors going to the a discrete CAP, while the DQS signals go to arrays.

 

** WARNING ** : U1.AA51 pin of M_A_DQS7 net does not have opposite pin although net is supposed to be differential

** WARNING ** : U1.AB52 pin of M_A_DQS7 net does not have opposite pin although net is supposed to be differential

** WARNING ** : U1.M48 pin of M_A_CK0_DP net does not have opposite pin although net is supposed to be differential

** WARNING ** : U1.M50 pin of M_A_CK0_DP net does not have opposite pin although net is supposed to be differential

 

Audit for the net: M_A_CK0_DP with type: W1_Slow

** Error **: Too many drivers, not allowed in the DDR interface! Driving pins: U1.M48, U1.M50

** Info **: Initialization of drivers failed!

NEXT RUN INFORMATION

**********************************************************************

Audit for the net: M_A_DQS0 with type: W1_Slow

** Error **: Too many drivers, not allowed in the DDR interface! Driving pins: U1.K38, U1.J38

** Info **: Initialization of drivers failed!

NEXT RUN INFORMATION

**********************************************************************

Audit for the net: M_A_DQS0 with type: R(1,1)_Slow

 

 

 

AUDITOR ERRORS REPORT

**********************************************************************

  Net M_A_CK0_DP:

        Too many drivers, not allowed in the DDR interface! Driving pins: U1.M48, U1.M50

  Net M_A_DQS0:

        Too many drivers, not allowed in the DDR interface! Driving pins: U1.K38, U1.J38

  Net M_A_DQS1:

        Too many drivers, not allowed in the DDR interface! Driving pins: U1.B34, U1.C35

  Net M_A_DQS2:

        Too many drivers, not allowed in the DDR interface! Driving pins: U1.F40, U1.D40

  Net M_A_DQS3:

        Too many drivers, not allowed in the DDR interface! Driving pins: U1.C43, U1.B44

  Net M_A_DQS4:

        Too many drivers, not allowed in the DDR interface! Driving pins: U1.M52, U1.N53

  Net M_A_DQS5:

        Too many drivers, not allowed in the DDR interface! Driving pins: U1.T44, U1.T42

  Net M_A_DQS6:

        Too many drivers, not allowed in the DDR interface! Driving pins: U1.Y48, U1.Y47

  Net M_A_DQS7:

        Too many drivers, not allowed in the DDR interface! Driving pins: U1.AA51, U1.AB52

Outcomes