9 Replies Latest reply on Aug 28, 2015 2:27 PM by mvgohil

    Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer

    mvgohil

      Hi,

       

      I have designed the schematics in dx designer. Now I am generating the cadence allegro compatible netlist but I am having below error.

      ***********************************************************************************************************************************************

      pcb: Note 6057: design sym CONNECTOR:CONN_3N-1: VALUE=CONN,ELEC: Bad property value

      pcb: Error 6034: Illegal character

       

      pcb: Error 6079: design sym ICS:PACKETENG_560_8: PINSWAP=(SPARE_8,SPARE_7,SPARE_6,SPARE_5,SPARE_4,SPARE_3,SPARE_2,SPARE_1,SPARE_12,SPARE_11,SPARE_10,SPARE_9): Hetero device property conflict

      pcb: Error 6079: design sym ICS:PACKETENG_560_12: PINSWAP=(NC_30,NC_29,NC_28,NC_27,NC_58,NC_26,NC_57,NC_25,NC_56,NC_24,NC_55,NC_23,NC_54,NC_22,NC_53,NC_21,NC_52,NC_20,NC_51,NC_50,NC_19,NC_18,NC_49,NC_17,NC_48,NC_16,NC_47,NC_15,NC_46,NC_14,NC_45,NC_13,NC_44,NC_12,NC_43,NC_11,NC_42,NC_9,NC_10,NC_41,NC_8,NC_40,NC_7,NC_6,NC_5,NC_4,NC_3,NC_2,NC_1,NC_39,NC_38,NC_37,NC_36,NC_35,NC_34,NC_33,NC_32,NC_31): Hetero device property conflict

      *******************************************************************************************************************************

      I have attached xls and high lighted errors with yellow color.

       

      These are the known error as dx designer help it self provides the solution as given below

      ========================

      PCB-6034

      Message:  Illegal character [character]. 

      Cause:  The attribute value indicated in the following message contains the illegal character shown. 

      Solution:  Fix the attribute value, enable automatic fixups, add a GENVAL fixup, or change the PCB configuration file to allow this character. PCB Configuration File: CHKVAL _NAME_CHK, CHKVAL _LIST_CHK, GENVAL. 

      ===============================================

      But I dont know how to implement the solution in design.

       

      I tried to solve by searching value "CONN,ELEC" in design and yes this is symbol name of connector. So do I need to change the name of symbol ? Because there are lots of instance are there.

       

      Please suggest a better solution.

       

      -

      Thanks,

      mahesh

        • 1. Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer
          mvgohil

          I have changed the configuration file and illegal character errors are gone.

           

          Still there are PINSWAP hertero device conflict error is there.

           

          In my design now there are 5 error while generating allegro netlist. Could anyone know where will be the device files ? I could not find the device file in my working directory. I can export the .tel file but no device file is there.

           

          Am I missing any setting in dxdesigner? Can anyone know about about howto generate the device files for allegro?

          • 2. Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer
            robert_davies

            It won't generate any outputs whilst you have errors in the schematic, you need to correct all errors before you can proceed. Looking at the errors the bad name error is due to the symbol name being 2INDDIO-B.n1 you can only have numbers after the decimal point as in 2INDDIO-B.1 etc.

            It also looks like one error is caused because you have a space in the name of a component TIE BAR.

            Not sure on the Hetero error, but it might be because you have pin swaps across devices.

            • 3. Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer
              mvgohil

              OK. we can not modify the symbol. But I could generate the netlist for PADs with 0 Error and many warning like below

              ======================================

              Warning 6113: Device 184-0518-070 has 0 shapes

              =====================================

              Can you please tell me which property should I modify to point the PCB foot print of each component. How to add the PCB footprint name.

               

              A flow of dxdesinger to PADs layout flow idea..

               

              -

              Thanks!

              • 5. Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer
                mvgohil

                Yes, You are correct.

                 

                I was able to generate the .tel and devices files after resolving all the error. But while importing it shows me below error,

                ==============================

                ! '705-3215-260' ! '100k' ;  R467

                                            ^

                ERROR(SPMHNI-67): Cannot find device file for '705-3215-260'.

                -------------------------------------------------------------------------------

                ! '351-6804-610' ! 'TPS53316RGTT' ;  U46 U45 U47

                                                    ^

                ERROR(SPMHNI-67): Cannot find device file for '351-6804-610'.

                -------------------------------------------------------------------------------

                ========================================================

                 

                But my devices for resistor is as below,

                 

                ========================================

                (Device file for RES-H)

                CLASS IC

                PINCOUNT 2

                PINORDER RES-H M P

                PINUSE RES-H BI BI

                FUNCTION G1 RES-H 2 1

                PACKAGEPROP VALUE VALUE

                END

                =======================================

                 

                here "705-3215-260" is part no,

                100L = value

                R467= ref des in .tel

                 

                while RES-H is symbol name. Foot print name is "040X020S2" which is not showing in .tel file and also there is not any link between .tel and device file. I think my configuration file has problem.

                 

                can you please suggest the changes needs to be done in allegro.cfg file for proper linking of .tel (having = footprint) to device file show the error can be removed?

                 

                2) And another error is extra exclamation sign. can you please suggest the changes to remove it ?

                ERROR(SPMHNI-62): Expected '!' before device, line ignored.

                -------------------------------------------------------------------------------

                R76 R74 R34 R36 R49 R28 R45 R1717 R65 R46 R33 R417 R69 R71 R35 R70 R56 R68,

                • 6. Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer
                  robert_davies

                  I can't help any further on this issues I suggest you contact your customer support representative and log a ticket.

                  • 7. Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer
                    mvgohil

                    Ok. We will initiate the thread with support team.

                     

                    meanwhile I have generated netlist for PADs. it is generating netlist with 0 error.

                     

                    I have put below property in attribute

                     

                    DEVICE = our parts 10 digit no (like : C1 184-0518-070)

                    PKG_TYPE = component FP name ( FP name=CT2917)

                     

                    Here is my ascii file,

                    ====

                    !PADS-POWERPCB-V9.0-MILS!

                     

                     

                    *PART*

                    C1 184-0518-070@CT2917

                    C2 184-0518-070@ct2917

                    C3 184-0518-070@ct2917

                    C5 184-6344-230@CT2917

                    C9 184-6344-230@CT291

                    ============================

                    Without PKG_TYPE attribute it generates  below method. it shows the attribute instead of PKG_TYPE.

                    C1 184-0518-070

                     

                    Can you please help me on this ?

                    • 8. Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer
                      mvgohil

                      I can not able to import below Ascii file

                       

                      ====

                      C1 184-0518-070@CT2917

                      C2 184-0518-070@ct2917

                      ===

                       

                      But I am able to import below ascii file in pads

                      ====

                      C1 CT2917

                      C2 ct2917

                       

                      Can you please guide me am I missing any setting while importing the in PADs generating netlist from DxD ?

                      • 9. Re: Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer
                        mvgohil

                        I think, I have solved the prob. In my lib Part type and decal name are same.

                         

                        While Part type should be 184-0518-070 and decal name should be CT2917. I tried with one component and it able to import it. Thanks!