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Error on generation of Cadence Allegro 15.Xx netlist generated from DX designer

Question asked by mvgohil on Aug 20, 2015
Latest reply on Aug 28, 2015 by mvgohil



I have designed the schematics in dx designer. Now I am generating the cadence allegro compatible netlist but I am having below error.


pcb: Note 6057: design sym CONNECTOR:CONN_3N-1: VALUE=CONN,ELEC: Bad property value

pcb: Error 6034: Illegal character


pcb: Error 6079: design sym ICS:PACKETENG_560_8: PINSWAP=(SPARE_8,SPARE_7,SPARE_6,SPARE_5,SPARE_4,SPARE_3,SPARE_2,SPARE_1,SPARE_12,SPARE_11,SPARE_10,SPARE_9): Hetero device property conflict

pcb: Error 6079: design sym ICS:PACKETENG_560_12: PINSWAP=(NC_30,NC_29,NC_28,NC_27,NC_58,NC_26,NC_57,NC_25,NC_56,NC_24,NC_55,NC_23,NC_54,NC_22,NC_53,NC_21,NC_52,NC_20,NC_51,NC_50,NC_19,NC_18,NC_49,NC_17,NC_48,NC_16,NC_47,NC_15,NC_46,NC_14,NC_45,NC_13,NC_44,NC_12,NC_43,NC_11,NC_42,NC_9,NC_10,NC_41,NC_8,NC_40,NC_7,NC_6,NC_5,NC_4,NC_3,NC_2,NC_1,NC_39,NC_38,NC_37,NC_36,NC_35,NC_34,NC_33,NC_32,NC_31): Hetero device property conflict


I have attached xls and high lighted errors with yellow color.


These are the known error as dx designer help it self provides the solution as given below



Message:  Illegal character [character]. 

Cause:  The attribute value indicated in the following message contains the illegal character shown. 

Solution:  Fix the attribute value, enable automatic fixups, add a GENVAL fixup, or change the PCB configuration file to allow this character. PCB Configuration File: CHKVAL _NAME_CHK, CHKVAL _LIST_CHK, GENVAL. 


But I dont know how to implement the solution in design.


I tried to solve by searching value "CONN,ELEC" in design and yes this is symbol name of connector. So do I need to change the name of symbol ? Because there are lots of instance are there.


Please suggest a better solution.