I made some tests.
The problem seems to be a net which is transferred between blocks and ended with a generic pin symbol which doesn't have NETNAME attributes or pintype IN / OUT definitions.
When I replaced the generic pin symbol with in- or out-symbol and added NETNAME, no extra pins were generated during conversion.
The extra pins were not really an error. The netlist remained correct with those pins. However, it added many (useless) pages and made the schematic look ugly.