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vsim elaboration with UVM tests

Question asked by bonifac on Sep 25, 2015

Hi all,


I have a SystemVerilog UVM environment and I use elaboration with vsim, because the DUT and the environment are quite huge. I am looking for a way to be able to develop/debug UVM tests without huge compile/opt/load times.


I have found in the documentation that I can change the stimulus (with filemap and sv_seed) and still use the elaborated environment. I want to do something similar: make some modifications in the SystemVerilog testfile and load it on top of the elaborated environment.


Is this possible to do? Does anyone have a solution or workaround for this?