3 Replies Latest reply on Jun 2, 2009 10:18 AM by jimmy.nguyen

    Question on full chip LVS with Calibre after dummy fill.

    rbhamare

       

      I have full chip LVS clean with certain hcell list.

       

       

      After adding DUMMY (od/poly) DOD/DPO fill polygons at chip level, its not coming clean.  creating "chip.sp" and  compare both take excessive runtime times.

       

       

      I observed that "chip.sp" file is now double the size (150Mb vs 70Mb ), so looks like hierarchy is messed up with seed promotions after adding fills.

       

       

      what is the common practice for clearing full chip lvs after adding fill ?  I mean is there any calibre switch or rule deck statement  used to treat these fill polygons so that it does not modify hierarchy /seed promotions?

       

       

      (I have od/po in base layer statment, not dod/dpo)

       

       

      Thanks,

       

       

      Rajendra Bhamare

       

       

        • 1. Re: Question on full chip LVS with Calibre after dummy fill.
          chris_balcom

          I've often wondered if it would be beneficial to pre-filter dummy fill, so that it didn't exist in the connectivity layers (with proper precautions for cases where it accidentally affects the connectivity).

           

          Instead of using drawn metal1 for instance, what if we used something like this:

           

           

          METAL1_C = ((DRAWN_METAL1 not interact CONT) not interact VIA1)

           

           

          METAL2_C = ((DRAWN_METAL2 not interact VIA1) not interact VIA2)

           

           

          etc. etc. for all dummy layers. Then use METAL1_C and METAL2_C in the CONNECT statements rather than a drawn metal layer that includes dummy metal.

           

           

          Anybody know if this has been tried, or if there are risks I haven't considered? (or if it's ineffective?)

          • 2. Re: Question on full chip LVS with Calibre after dummy fill.
            banderson

             

            This may seem like an odd question, but why do you run lvs on the design after it is clean?

             

             

            Let me walk you through why.

             

             

            The fill needs to be checked by drc. As part of your fill rule set, you need to OR every single layer

             

             

            that has devices on it such as all_layers_with_stuff_on_it = all_layers ORmetal_block_layer

             

             

            Then to be safe, you need to create a safety zone to prevent drc violations by

             

             

            growing all_layers_with_stuff_on_it by say 5 microns in all directions

             

             

            after you create this layer, then start your fill process

             

             

            metal1_fill = metal1 NOT all_layers_with_stuff_on_it

             

             

            then form the fill into nice polygons that you want fill with with metal1 and so on for your metal and poly layers.

             

             

            So, basically, fill will never touch any layer with components on it.  Even OD and POLY are part of your

             

             

            all layer operation and grow it.

             

             

             

             

             

            I hope this helps, and I hope I didn't underestimate the problem. Best regards, Brien

             

             

            • 3. Re: Question on full chip LVS with Calibre after dummy fill.
              jimmy.nguyen

              run the metal , OD/PO fill flat instead of hier, then put the fill back on the final gds. Run the LVS again your lvs should be clean

              I think there is some thing wrong the fill program some time it does not work on some design, but if you the the fill flat it always work

              the down site is your run time is a lot longer

              Jimmy