Hi, I am Brien Anderson from Synaptics. Please let me know if there is a FAQ for this forum, especially for Cadence inherited connections.
Please contact me if you are able to get Calibre lvs to work with Cadence Virtuoso Schematic/layout inherited connections.
Does anyone know if there is a Calibre equivalent of the Assura commend joinNets ?
usage is something such as
joinNets analog_section AGND GND!
joinNets digital_section DGND GND!
Where GND! is an inherited connection, but it resolves into analog ground AGND for the analog_section only, and digital ground DGND for the digital_section only. There are shared sub cells between analog_section
and digital_section such as NAND2. Thus the use of VDD! GND! inherited connections.
The actual primary ports of the chip are DGND, AGND, and not VDD! nor GND!.
Thank you in advance.
Best regards, Brien
Hi Brien. Welcome to the forums. You might want to repost your question in its own thread, since people might not read it here in this introduction thread.
I'm not familiar with joinNets in Assura. How is analog_section denoted? Is it a marker layer?