banderson

Calibre LVS of Cadence inherited connections or Assura joinNets command ?

Discussion created by banderson on Feb 2, 2009
Latest reply on Feb 12, 2009 by banderson

Does anyone have an app note on how to get Calibre LVS to recognize Cadence inherited connections?

 

I have a design that uses a standard cell library with power and ground assigned as VDD! and GND!

The schematic, synthesis, and layout use the same standard cell library.

 

The base cells are used in different SUBCKTs of the design such as analog_section and digital_section.

The power connections are different in each section or subckt.

 

Example: in the design, I have SUBCKT analog_section VDD! GND!

 

that is connected to

 

Xi_analog_section AVDD AGND

 

where all of the standard cells such as or, and, nand, logic etc have the inherited

power connections resolved to AVDD and AGND in the analog_section block

 

 

and also SUBCKT digital_section VDD! GND!

 

that is connected to

 

Xi_digital_section DVDD DGND

 

where all of the standard cells such as or, and, nand, logic etc have the inherited

power connections resolved to DVDD and DGND in the digital_section block

 

 

Assura matches the lvs by the use of the joinNets command, simply used as

joinNets analog_section VDD! AVDD

joinNets digital_section VDD! DVDD

and so on

 

 

 

Does anyone know if Calibre has the equivalent of a join nets command on a per subckt basis?

Are there other tricks that I should be using in the cdl netlist to get Calibre to resolved

inherited connections? Thanks in advance.

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