6 Replies Latest reply on Feb 15, 2009 7:00 AM by banderson

    Calibre LVS of Cadence inherited connections or Assura joinNets command ?

    banderson

      Does anyone have an app note on how to get Calibre LVS to recognize Cadence inherited connections?

       

      I have a design that uses a standard cell library with power and ground assigned as VDD! and GND!

      The schematic, synthesis, and layout use the same standard cell library.

       

      The base cells are used in different SUBCKTs of the design such as analog_section and digital_section.

      The power connections are different in each section or subckt.

       

      Example: in the design, I have SUBCKT analog_section VDD! GND!

       

      that is connected to

       

      Xi_analog_section AVDD AGND

       

      where all of the standard cells such as or, and, nand, logic etc have the inherited

      power connections resolved to AVDD and AGND in the analog_section block

       

       

      and also SUBCKT digital_section VDD! GND!

       

      that is connected to

       

      Xi_digital_section DVDD DGND

       

      where all of the standard cells such as or, and, nand, logic etc have the inherited

      power connections resolved to DVDD and DGND in the digital_section block

       

       

      Assura matches the lvs by the use of the joinNets command, simply used as

      joinNets analog_section VDD! AVDD

      joinNets digital_section VDD! DVDD

      and so on

       

       

       

      Does anyone know if Calibre has the equivalent of a join nets command on a per subckt basis?

      Are there other tricks that I should be using in the cdl netlist to get Calibre to resolved

      inherited connections? Thanks in advance.

        • 1. Re: Calibre LVS of Cadence inherited connections or Assura joinNets command ?
          rbhamare

           

          Try this:

           

           

          I am mot aware of statements to join different nets, but this is how it can be achieved.  You can rename the text during LVS run without modifying the actual layout.

           

           

          LAYOUT RENAME TEXT "/VDD!/AVDD/g"

           

           

          If you want to restrict it so some cells, then define cell list:

           

           

          LAYOUT CELL LIST analog_section cell1 cell2

           

           

          LAYOUT RENAME TEXT "/VDD!/AVDD/g" CELL LIST analog_section

           

           

          Thanks,

           

           

          Rajendra

           

           

          • 2. Re: Calibre LVS of Cadence inherited connections or Assura joinNets command ?
            karen_chow

            The SVRF command VIRTUAL CONNECT  NAME net1 net2 maybe of use.

            • 3. Re: Calibre LVS of Cadence inherited connections or Assura joinNets command ?
              banderson

               

              Thanks Rajendra,

               

               

               

               

               

              We tried the layout rename text on a analog_section and also the digital_section basis,

               

               

              and it did not work.

               

               

               

               

               

              The layout does not have VDD! and GND! only the source schematic (cdl netlist).

               

               

              The layout is connected correctly, the problem is using multiple power supplies

               

               

              in the source.

               

               

               

               

               

              Does anyone have any experience with inherited connections?

               

               

               

               

               

              Thanks again.

               

               

               

               

               

              Best regards, Brien

               

               

              • 4. Re: Calibre LVS of Cadence inherited connections or Assura joinNets command ?
                banderson

                 

                Thanks Karen,

                 

                 

                This may work if you can set the command on a per SUBCKT basis.

                 

                 

                The VDD! is not the same as VDD:

                 

                 

                VDD: is a virtual connection, VDD! is an inherited connection.

                 

                 

                Typically, unless you specify what netset property you use for VDD!, the default will be VDD.

                 

                 

                If all power in a standard cell library all uses the same VDD, then there is no problem and life is good.

                 

                 

                However, if you use many VDD: in many different blocks, and you specify a different VDD! netset property

                 

                 

                for each block such as VDD! for the analog_section = AVDD, and VDD! for the digital_section = DVDD,

                 

                 

                then how you specify the virtual connection for VDD: in each block becomes interesting.

                 

                 

                There must be an app note somewhere for how to use Calibre LVS with Cadence Virtuoso inherited connection flow.

                 

                 

                Thank you very much.

                 

                 

                 

                 

                 

                Brien

                 

                 

                • 5. Re: Calibre LVS of Cadence inherited connections or Assura joinNets command ?
                  chris_balcom

                   

                  Hi Brien,

                   

                   

                  As I understand it, Cadence offers explicit inherited connections and they also offer implicit inherited connections. I've also seen the phrase "net expressions on global nets" which may be just another way of referring to implicit inherited connections. The point I'd like to add to the discussion is that Calibre uses the netlist, not the schematic. Since Calibre uses the netlist it really comes down to how the netlist is constructed. If you could share a simplified netlist showing the key points, maybe 10 to 30 lines or so just to give everyone an idea of what your netlist looks like we should be able to quickly focus on a problem area.

                   

                   

                  I can offer an expert opinion on how Calibre will work with a netlist example you could provide, and maybe someone else could offer an expert opinion on how to control your Cadence netlister in case adjustments are necessary to get the optimal netlist in your case.

                   

                   

                  Best regards,

                  -chris

                   

                   

                  • 6. Re: Calibre LVS of Cadence inherited connections or Assura joinNets command ?
                    banderson

                    Thanks Chris, please see attached cdl netlist. The inh_GND resolves to AGND in the analog_section and DGND in the digital_section.

                    The inh_VDD resolves to AVDD in the analog_section, and DVDD in the digital_section. Also notice the use of inh_VDD

                    as an internal node to mimic the verilog in of a netlist from place and route that uses VDD! as supply1 tie off- the connection in the cdl netlist is inh_VDD.

                    Also note how to spice things up, DVDD and DGND are added as pins and not inherited connections to the analog section to supply power to one digital circuit in the

                    analog_section.

                     

                    {code}

                    ************************************************************************
                    * auCdl Netlist:
                    * Library Name:  test_lib
                    * Top Cell Name: calibre_debug_chip
                    * View Name:     schematic
                    ************************************************************************

                     

                    *.EQUATION
                    *.SCALE METER
                    *.MEGA

                     

                    ************************************************************************
                    * Library Name: stdcells
                    * Cell Name:    NR2D0
                    * View Name:    schematic
                    ************************************************************************

                     

                    .SUBCKT NR2D0 A1 A2 ZN inh_GND inh_VDD
                    MM3 ZN A2 U2_U4_SOURCE inh_VDD P W=3.5E-06 L=3.5E-07 m=1
                    MM4 U2_U4_SOURCE A1 inh_VDD inh_VDD P W=3.5E-06 L=3.5E-07 m=1
                    MM2 ZN A2 inh_GND inh_GND N W=1E-06 L=3.5E-07 m=1
                    MM1 ZN A1 inh_GND inh_GND N W=1E-06 L=3.5E-07 m=1
                    .ENDS

                     

                    ************************************************************************
                    * Library Name: stdcells
                    * Cell Name:    ND2D0
                    * View Name:    schematic
                    ************************************************************************

                     

                    .SUBCKT ND2D0 A1 A2 ZN inh_GND inh_VDD
                    MM3 ZN A1 U6_SOURCE inh_GND N W=2E-06 L=3.5E-07 m=1
                    MM4 U6_SOURCE A2 inh_GND inh_GND N W=2E-06 L=3.5E-07 m=1
                    MM2 ZN A1 inh_VDD inh_VDD P W=2.5E-06 L=3.5E-07 m=1
                    MM1 ZN A2 inh_VDD inh_VDD P W=2.5E-06 L=3.5E-07 m=1
                    .ENDS

                     

                    ************************************************************************
                    * Library Name: test_lib
                    * Cell Name:    calibre_debug_analog_timing
                    * View Name:    schematic
                    ************************************************************************

                    .SUBCKT calibre_debug_analog_timing in1 in2 out1 inh_VDD inh_GND
                    Xi_nor net8 inh_VDD out1 inh_GND inh_VDD / NR2D0
                    Xi_nand in1 in2 net8 inh_GND inh_VDD / ND2D0
                    .ENDS

                     

                    ************************************************************************
                    * Library Name: t1320_main
                    * Cell Name:    dac_buf
                    * View Name:    schematic
                    ************************************************************************

                     

                    .SUBCKT dac_buf GND VDD minus nbias out plus
                    Mmpout out mir VDD VDD PLVT W=2u L=4.5u m=1
                    Mmpmir mir mir VDD VDD PLVT W=2u L=4.5u m=1
                    Mmtail tail nbias GND GND N W=2u L=2u m=1
                    Mmminus out minus tail GND N W=2u L=3u m=1
                    Mmplus mir plus tail GND N W=2u L=3u m=1
                    .ENDS

                     

                    ************************************************************************
                    * Library Name: test_lib
                    * Cell Name:    calibre_debug_analog_section
                    * View Name:    schematic
                    ************************************************************************

                     

                    .SUBCKT calibre_debug_analog_section DGND DVDD GND VDD in2 in_a in_b out1
                    + inh_GND inh_VDD
                    MM1 net018 in_b DGND DGND N W=2u L=350.00n m=1
                    MM0 net018 in_b DVDD DVDD P W=2u L=350.00n m=1
                    Xi_at in_a net018 net11 inh_VDD inh_GND / calibre_debug_analog_timing
                    Xi_dac_buf GND VDD in2 in2 out1 net11 / dac_buf
                    .ENDS

                     

                    ************************************************************************
                    * Library Name: test_lib
                    * Cell Name:    calibre_debug_digital_section
                    * View Name:    schematic
                    ************************************************************************

                     

                    .SUBCKT calibre_debug_digital_section in1 in2 out1 inh_VDD inh_GND
                    Xi_nor net8 inh_VDD out1 inh_GND inh_VDD / NR2D0
                    Xi_nand in1 in2 net8 inh_GND inh_VDD / ND2D0
                    .ENDS

                     

                    ************************************************************************
                    * Library Name: test_lib
                    * Cell Name:    calibre_debug_core
                    * View Name:    schematic
                    **********************************************************************

                     

                    .SUBCKT calibre_debug_core AGND ASIN1 ASIN2 ASIN4 ASOUT AVDD DGND DSIN1 DSIN2
                    + DSOUT DVDD
                    Xi_analog_section DGND DVDD AGND AVDD ASIN4 ASIN1 ASIN2 ASOUT AGND AVDD /
                    + calibre_debug_analog_section
                    Xi_digital_section DSIN1 DSIN2 DSOUT DVDD DGND / calibre_debug_digital_section
                    .ENDS

                     

                    ************************************************************************
                    * Library Name: test_lib
                    * Cell Name:    calibre_debug_chip
                    * View Name:    schematic
                    ************************************************************************

                     

                    .SUBCKT calibre_debug_chip AGND ASIN1 ASIN2 ASIN4 ASOUT AVDD DGND DSIN1 DSIN2
                    + DSOUT DVDD

                     

                    XI0 AGND ASIN1 ASIN2 ASIN4 ASOUT AVDD DGND DSIN1 DSIN2 DSOUT DVDD /
                    + calibre_debug_core
                    .ENDS

                    {code}