2 Replies Latest reply on Oct 8, 2015 10:00 AM by lalit.bhambhani@panavision.com

    HDL Designer




      First of all, I'm not sure if this is the correct forum to ask this questions.  But the IC Design section made sense to post regarding HDL Designer 2015.a1(Build 3).

      If its the wrong forum, please point me to the correct one.


      I'm working with HDL Designer and getting an error message.  I'm trying to generate a visualization blocks and importing exiting Verilog source files for Xilinx Virtex 6 project.

      Every file I import has parameters declared which are used in the module and HDL Designer is throwing an error on every single one.


      example is


      module mod_name #


           param1 = 32;          // <- error message here

           param2 = 64;          // <- error message here



      input [param1 - 1:0] a;

      output [param2 -1 :0] b;




      What could be the cause of the error?  There is no real information, the violation report only says

      "Line x: ERROR, Syntax error near (param1)"


      I don't see anything wrong with the syntax.  Is there some option in the tool I need to enable?


      Thanks You.