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Eembeded capacitive P/G plane pairs or Use normal Capcactors?

Discussion created by yu.yanfeng on Feb 5, 2009
Latest reply on Mar 5, 2009 by yu.yanfeng

PI is hot now. I have watched there are many are evaluating embeded capacitive material such as 3M c-ply and Oak-MitsuiFaradFlex. We have evualated these material 2 years ago and fabed sample.It can provide additional PI advantage compare to normal thin core. but it's cost isn't feasible to widely adopt it. Most of PI may be dressed by a good design of Power filtering. I have seen many designer never carefully desing thier power dilivering rail and some of design have inherient prolem with thier wrong filtering topology. I think it's first step for PI  to better use normal capacitors instead of  using embedded capcitive material. Such tools as Hyperlynx PI will make design tradeoff easy and fast.


    • Kenneth_Wood


      It depends on the cost of the new material and it's ROI in terms of performance.



      The 3M material is only 10 nF/in2 so one 0.1uF cap could easily swamp out the effects of this on a small board.



      I think the advantages of this material really direct themselves to applications that do not require heavy amounts of capacitance and could benefit



      from the reduced part count thereby increasing density.






      • strangd


        I don't believe that it is a one for one pF comparison of the capacitance between the power plane which is feeding charge to the parts and the by pass capacitor which is replenishing the charge on the planes.   Properly located power planes are more effective at the leading edge of the rise of the signals.  As the rise times get shorter the apparent distance to a bypass cap seams farther and father away from your switching device.  I my not beleive the 10 to 1 effectiveness that I have read but certainly principal is sound.






        • yu.yanfeng

          Yes. P/G plane paris is so important to deal with IC with very sharp Delta I/ Delta t. What I means is that a good methodology should begin with Bypass caps to cover PI in mid -frequecy segament, then consider to deal with PI in higher-frequency segament where embeded capacitive P/G is valid. Without a good Bypass placement, it's no effecitve and money waste to adopt embeded material.

          • Mentor_Per_Viklund

            I find this article by Rick Ulrich from Univ. of Arkansas immensly interesting.

            He claims that using high Er materials such as C-Ply and others may not be beneficial.



            Reason being that the higher the Er the slower response resulting in larger plane regions needed to decouple a circuit.

            In fact, he presents a formula indicating that the ER is elliminated in the calculation of required capacitance plane area.


            This would mean that using a thin dielectric is the sole factor for embedded capacitance plane ability to supply a charge to a circuit.


            As said, well defined decoupling networks will perform well without embedded capacitance planes but its really only true up to certain signal speeds where the cap is not able to deliver its charge fast enough.

            We see on very high speed boards that very narrow dielectric between pwr/gnd significantly improves the bandwidth of the power grid and we actually
            built a test vehicle some years ago using c-ply where managed to remove over 800 discrete capacitors and still have a fully functioning board.

            Cost went up with C-ply but the cost of procuring, stocking, assembling 800 caps also counts as well as removing this number of parts enabled layer reduction and change from dual sided to single sided assembly.


            I'm sure it will be along time before we can announce the death of the discrete decoupling cap but or some designs we do see sharply reduced numbers already now.




            • yu.yanfeng

              Published by Eric Bogatin on 03 Feb 2009

              2/3/09 The Light Just Spread to a Larger Circle with Mentor’s Release of HyperLynx 8.0

              There is an old joke about the guy who dropped a diamond ring on the ground one night. He’s down on his knees looking for it and another fellow comes along and asks to help. They’re both down on their knees for a few minutes with no luck. The stranger then says, “I can’t find it anywhere. Where did you drop it?”

              The other guy says, “I dropped it over there,” pointing ten feet away. The stranger replies, “If you dropped it over there, why are you looking over here?” He replies, “Because the lights better over here.”

              I think this story illustrates one of the limitations of traditional power integrity analysis. We tend to do what is easy, where the light is, rather than tackle the real questions, because they are hard.

              Doing a simple SPICE simulation of the impedance profile of a collection of capacitors is easy, and every engineer should be doing this. But, taking the next step to explore the interaction of the capacitors and the planes, or how the mounting geometry influences the ESL and the resulting impedance profile, is hard. The only tool that will take into account the arbitrary, odd shaped power and ground planes, a fact of life in real world product design, is a 3D field solver.

              While many of these tools have jewels of insight hidden within them, they are positioned ten feet away from most engineers, in the darkness. They are hard to understand, hard to use, hard to evaluate if the answer is correct or not, and take a while to spin through a lot of what ifs.

              I think the recent announcement by Mentor Graphics at DesignCon 2009, of the release of HyperLynx 8.0, which includes power integrity analysis, now expands the circle of light into the power integrity world. Since its first release more than 15 years ago, HyperLynx has been an incredibly easy to use circuit simulator. With the inclusion of lossy line models and eye diagrams, it enables high speed serial link simulation to greater than 10 Gbps.

              This easy to use interface and fast computation speed has been extended to power integrity analysis. Now it is easy to evaluate questions like, does position really matter? What is the impact of a Swiss cheese clearance hole field on the impedance of the decoupling capacitor? What is the impedance profile of the capacitors and the planes? Up to what frequency or rise time are decoupling capacitors really effective? For an odd, irregular shaped power plane, what is the DC resistance and are there any hot spots?

              I’ve had the opportunity to take the beta version for a test drive and I think it will dramatically reduce the fear, uncertainty and doubt of designing the power distribution network in your design.











              Also I have a chance to use Beta HL 8.0. I agree with Eric's comment. This is an easy to use and easy to understand PI Tool, will bring productivity to board designer. One of the weakness I saw in Beta HL 8.0 is the poor performance of  scratching pre-layout planes










              • Steve_McKinney

                Hi Yanfeng,


                Can you elaborate on your comment in your post:



                yu.yanfeng wrote:


                .....One of the weakness I saw in Beta HL 8.0 is the poor performance of  scratching pre-layout planes











                I'd like to capture what it is you perceive as poor performance and find out suggestions for improvements.

                • yu.yanfeng



                  There are a lot of topics to talk about how to improve the pre-layout planes scratching in the Beta  and I  wish to check it  in the coming formal release.