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ddr read batch simulation

Question asked by agxinmj on Dec 6, 2015


             In ddr3 batch the write leveling option is present ,similarly how or where  read leveling settings are  fed to the simulation engine ?

Read leveling is implemented in the qoriq power pc as CAS to preamble calibration and dq to dqs calibration is there any option incorporated in the new release of hyperlynx 9.2