2 Replies Latest reply on Mar 16, 2016 2:52 PM by danmc

    calibreview vs cadence netSet expressions

    danmc

      I am trying to figure out if there is an inherent limitation in the tools or if this is a pilot error.  I have a cell, "mycell" with schematic, symbol, and layout views in the Cadence virtuoso environment.  The block is a small custom logic block consisting of only standard cell instances.  For the sake of discussion, let's just call it 3 inverters in series.  The standard cell library symbols have power and ground pins but the pins have attached net expressions so when I instantiate them in a schematic I have 3 ways of connecting power and ground.

       

           1) use an explicit wire to the  symbol pin

           2) attach a netSet property like VDD=MYVDD and VSS=MYVSS to the instance

           3) Add pins to "mycell"  with an associated netexpression called "VDD" and "VSS" (these are the property names that the standard cell library uses).  Then when I instantiate "mycell" at a higher level I can either wire to its power/ground pins or use netSet's to define VDD and VSS and this is passed down the hierarchy.

       

      Options #1 and #2 are useful if you are dropping in an individual logic gate here and there in an analog schematic.  For example maybe you have a block with a shutdown pin and you also need shutdown_bar internally.

       

      Option #3 is useful for a block which is all logic gates.  Then you don't have to add netSet's all over the place or clutter up everything with power/ground wires.

       

      In my layout, the pin shapes correctly indicate that there are net expressions.  The text on the power pin ends up looking like [@VDD:%:vdd!].  This means that the net expression is VDD and it is currently evaluating to vdd! (the default in the absence of any netset).

       

      Assura LVS is fine, no problems.  QRC parasitic extraction and creation of an extracted view is fine, no problems.  All of the stuff related to the inherited pins works fine.

       

      For Calibre LVS to pass, I end up needing to add

      *.EQUIV VDD=vdd! VSS=vss!

      in my CDL file.

       

      When I create a calibre view for "mycell", it seems like it worked but then when I try to netlist a simulation testbench I find that the inherited power/ground pins were missing from the calibre view.   I'm not surprised because what I see in the svdb/mycell.cv file is:

       

      [snip]

      mgc_rve_cell_start "mycell" "VSS" "VDD" "OUT" "IN"

      [snip]

       

      which to me looks like the power/ground pins made it but there is nothing to tell mgc_rve_create_cellview() to include net expressions for those pins.

       

      Any comments?

       

      Thanks

      -Dan

        • 1. Re: calibreview vs cadence netSet expressions
          samantha_lizak

          Does your rule file include any Virtual Connect statements?  You probably need Virtual Connect Colon -- any net names that are identical before the colon are considered to be the same net - and Virtual Connect Name -- treats VDD and vdd as the same name.

           

          -Sam.

          • 2. Re: calibreview vs cadence netSet expressions
            danmc

            I don't think virtual connections are the way to go here.  That is for shorting disjoint nets of the same name instead of defining an equivalence. 

             

            Another way which can get past LVS is to add something like this:

             

            LAYOUT RENAME TEXT "/VDD/vdd!/g" "/VSS/vss!/g"

             

            However, calibre still doesn't seem to know what to do with inherited pins when creating the calibreview.

            PEX NETLIST "svdb/my_inv_inh.cv" CALIBREVIEW

            creates the calibreview netlist but there does not appear to be anything in the netlist indicating that some pins are inherited pins.